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july 2014 docid025118 rev 4 1 / 101 this is information on a product in full production. www.st.com stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 automotive 8 - bit mcu, with up to 8 kbytes flash, data eeprom, 10 - bit adc, timers, lin, spi, i2c, 3 to 5.5 v datasheet - production da ta features core ? 16 mhz advanced stm8 core with harvard architecture and 3 - stage pipeline ? extende d instruction set memories ? program memory: 4 to 8 kbytes flash; data retention 20 years at 55 c after 1 kcycles ? data memory: 640 bytes true data eeprom; endurance 300 kcycles ? ram: 1 kbytes clock management ? low - power crystal resonator oscillator with ex ternal clock input ? internal, user - trimmable 16 mhz rc and low - power 128 khz rc oscillators ? clock security system with clock monitor reset and supply management ? wait/auto - wakeup/halt low - power modes with user definable clock gating ? low consumption power - o n and power - down reset interrupt management ? nested interrupt controller with 32 interrupts ? up to 28 external interrupts on 7 vectors timers ? advanced control timer: 16 - bit, 4 capcom channels, 3 complementary outputs, dead - time insertion and flexible synch ronization ? 16 - bit general purpose timer, with 3 capcom channels (ic, oc or pwm) ? 8 - bit basic timer with 8 - bit prescaler ? auto wakeup timer ? window and independent watchdog timers communications interfaces ? linuart, lin 2.1 compliant, master/slave modes wi th automatic resynchronization ? spi interface up to 8 mbit/s or f master/2 ? i 2 c interface up to 400 kbit/s analog to digital converter (adc) ? 10 - bit, 1 lsb adc with up to 7 muxed channels + 1 internal channel, scan mode and analog watchdog ? internal referen ce voltage measurement i/os ? up to 28 i/os on a 32 - pin package including 21 high sink outputs ? highly robust i/o design, immune against current injection operating temperature up to 150 c qualification conforms to aec - q100 lqfp32 7x7 tssop20
contents stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 2 / 101 docid025118 rev 4 contents 1 introduction ................................ ................................ ..................... 8 2 description ................................ ................................ ....................... 9 3 block diagram ................................ ................................ ................ 10 4 product overview ................................ ................................ .......... 11 4.1 central processing unit stm8 ................................ ......................... 11 4.2 single wire interface mod ule (swim) and debug module (dm) ...... 12 4.3 interrupt controller ................................ ................................ ........... 12 4.4 flash program and data eeprom memory ................................ .... 12 4.5 clock controller ................................ ................................ ............... 14 4.6 power management ................................ ................................ ........ 15 4.7 watchdog timers ................................ ................................ ............. 15 4.8 auto wakeup counter ................................ ................................ ...... 16 4.9 beeper ................................ ................................ ............................ 16 4.10 tim1 - 16 - bit advanced control timer ................................ ............... 16 4.11 tim5 - 16 - bit general purpose timer ................................ ................ 16 4.12 tim6 - 8 - bit basic timer ................................ ................................ ... 17 4.13 analog - to - digital converter (adc1) ................................ ................. 17 4.14 communication interfaces ................................ ............................... 18 4.14.1 linuart ................................ ................................ .......................... 18 4.14.2 spi ................................ ................................ ................................ .... 19 4.14.3 i2c ................................ ................................ ................................ ..... 19 5 pinout and pin description ................................ ........................... 20 5.1 stm8af6213/STM8AF6223 tssop20 pinout ............................... 20 5.2 STM8AF6223pxax tssop20 pinout ................................ .............. 21 5.3 tssop20 pin description ................................ ................................ 21 5.4 stm8af6226 lqfp32 pinout ................................ ......................... 25 5.5 lqfp32 pin description ................................ ................................ ... 26 5.6 alternate function remapping ................................ .......................... 29 6 memory and register map ................................ ............................. 30 6.1 memory map ................................ ................................ ................... 30 6.2 register map ................................ ................................ ................... 31 6.2.1 i/o port hardware register map ................................ ........................ 31
stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 contents docid025118 rev 4 3 / 101 6.2.2 general hardw are register map ................................ ........................ 32 6.2.3 cpu/swim/debug module/interrupt controller registers .................. 39 7 interrupt vector mapping ................................ .............................. 41 8 option bytes ................................ ................................ .................. 42 8.1 stm8af6226/STM8AF6223/STM8AF6223a/stm8af6213 alternate function remapping bits ................................ ................................ . 45 9 electrical characteristics ................................ .............................. 50 9.1 parameter conditions ................................ ................................ ...... 50 9.1.1 minimum and maximum values ................................ ........................ 50 9.1.2 typical values ................................ ................................ ................... 50 9.1.3 typical curves ................................ ................................ ................... 50 9.1.4 loading capacitor ................................ ................................ ............. 50 9.1.5 pin input voltage ................................ ................................ ............... 51 9.2 absolute maximum ratings ................................ .............................. 51 9. 3 operating conditions ................................ ................................ ....... 53 9.3.1 vcap external capacitor ................................ ................................ .. 55 9.3.2 supply current characteristics ................................ .......................... 55 9.3.3 external clock sources and timing characteristics ............................ 65 9.3.4 internal clock sources and timing characteristics ............................. 68 9.3.5 memory characteristics ................................ ................................ ..... 69 9.3.6 i/o port pin characteristics ................................ ................................ 70 9.3.7 reset pin characteristics ................................ ................................ .. 77 9.3.8 spi serial peripheral interface ................................ .......................... 80 9.3.9 i2c interface characteristics ................................ ............................. 83 9.3.10 10 - bit adc characteristics ................................ ................................ 84 9.3.11 emc characteristics ................................ ................................ .......... 87 10 package information ................................ ................................ ..... 91 10.1 32 - pin lqfp package mechanical data ................................ .......... 91 10.2 20 - pin tssop package mechanical data ................................ ....... 92 11 thermal characteristics ................................ ................................ 94 11.1 reference document ................................ ................................ ....... 94 11.2 selecting the product temperature range ................................ ........ 95 12 ordering information ................................ ................................ ..... 96 13 stm8 development tools ................................ .............................. 97 13.1 emulation and in - c ircuit debugging tools ................................ ......... 97
contents stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 4 / 101 docid025118 rev 4 13.2 software tools ................................ ................................ ................. 98 13.2.1 stm8 toolset ................................ ................................ .................... 98 13.2.2 c and assembly toolchains ................................ .............................. 98 13.3 programming tools ................................ ................................ .......... 98 14 revision history ................................ ................................ ............ 99
stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 list of tables docid025118 rev 4 5 / 101 list of tables table 1: stm8af6226/STM8AF6223/STM8AF6223a/stm8af6213 ................................ ....................... 9 table 2: peripheral clock gating bit assignments in c lk_pckenr1/2 registers ................................ .... 14 table 3: tim timer features ................................ ................................ ................................ ....................... 17 table 4: communication peripheral naming correspondence ................................ ................................ .. 18 table 5: legend/abbreviations for pinout tables ................................ ................................ ....................... 20 table 6: stm8af6213/STM8AF6223 tssop20 pin description ................................ ............................. 21 table 7: STM8AF6223a tssop20 pin description ................................ ................................ .................. 23 table 8: lqfp32 pin description ................................ ................................ ................................ .............. 26 table 9: mem ory model for the device covered in this datasheet ................................ ............................ 31 table 10: i/o port hardware register map ................................ ................................ ................................ . 31 table 11: general hardware reg ister map ................................ ................................ ................................ 32 table 12: cpu/swim/debug module/interrupt controller registers ................................ .......................... 39 table 13: interrupt mapping ................................ ................................ ................................ ...................... 41 table 14: option bytes ................................ ................................ ................................ .............................. 42 table 15: option byte description ................................ ................................ ................................ ............. 43 table 16: stm8af622 6 alternate function remapping bits [7:2] for 32 - pin packages ............................. 45 table 17: stm8af6213/STM8AF6223 alternate function remapping bits [7:2] for 20 - pin packages ...... 46 table 18: STM8AF6223a alternate function remapping bits [7:2] for 20 - pin packages ........................... 47 table 19: stm8af6226 alternate function remapping bits [1:0] for 32 - pin pac kages ............................. 47 table 20: stm8af6213/STM8AF6223 alternate function remapping bits [1:0] for 20 - pin packages ...... 48 table 21: STM8AF6223a al ternate function remapping bits [1:0] for 20 - pin packages ........................... 49 table 22: voltage characteristics ................................ ................................ ................................ .............. 51 table 23: current characterist ics ................................ ................................ ................................ .............. 51 table 24: thermal characteristics ................................ ................................ ................................ ............. 52 table 25: operating lifetime (olf) ................................ ................................ ................................ ........... 52 table 26: general operating conditions ................................ ................................ ................................ .... 53 table 27: operating conditions at power - up/power - down ................................ ................................ ........ 54 table 28: t otal current consumption with code execution in run mode at vdd = 5 v ............................. 55 table 29: total current consumption with code execution in run mode at vdd = 3.3 v .......................... 56 table 30: total current consumption in wait mode at vdd = 5 v ................................ ............................. 57 table 31: total current consumption in wait mode at vdd = 3.3 v ................................ .......................... 58 table 32: total current consumption in active halt mode at vdd = 5 v ................................ ................... 58 table 33: total current consumption in active halt mode at vdd = 3.3 v ................................ ................ 59 table 34: total current consumption in halt mode at vdd = 5 v ................................ ............................. 60 table 35: total current consumption in halt mode at vdd = 3.3 v ................................ .......................... 60 table 36: wakeup times ................................ ................................ ................................ ........................... 61 table 37: total current consumption and timing in forced reset state ................................ ...................... 62 table 38: peripheral current consumption ................................ ................................ ................................ 62 table 39: hse user external clock characteristics ................................ ................................ ................... 65 tabl e 40: hse oscillator characteristics ................................ ................................ ................................ ... 66 table 41: hsi oscillator characteristics ................................ ................................ ................................ ..... 68 table 42: lsi oscillator characteristics ................................ ................................ ................................ ..... 68 table 43: ram and hardware registers ................................ ................................ ................................ .... 69 table 44: flash program memory/data eeprom memory ................................ ................................ ...... 69 table 45: flash program memory ................................ ................................ ................................ ............. 69 table 46: data memory ................................ ................................ ................................ ............................ 70 table 47: i/o static characteristics ................................ ................................ ................................ ............ 70 table 48: output driving current (standard ports) ................................ ................................ ..................... 72 table 49: output driving current (true open drain ports) ................................ ................................ .......... 72 table 50: output driving current (high sink ports) ................................ ................................ .................... 72 table 51: nrst pin characteristics ................................ ................................ ................................ .......... 77 table 52: spi characteristics ................................ ................................ ................................ .................... 80
list of tables stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 6 / 101 docid025118 rev 4 table 53: i2c characteristics ................................ ................................ ................................ .................... 83 table 54: adc characteristics ................................ ................................ ................................ .................. 84 table 55: adc accuracy with rain < 10 k , vdd= 5 v ................................ ................................ ......... 85 table 56: adc accuracy with rain < 10 k rain, vdd = 3.3 v ................................ ............................ 86 table 57: ems data ................................ ................................ ................................ ................................ .. 88 table 58: emi data ................................ ................................ ................................ ................................ .... 88 table 59: esd absolute maximum ratings ................................ ................................ ............................... 89 table 60: electrical sensitivities ................................ ................................ ................................ ................ 90 table 61: 32 - pin low profile quad flat package mechanical data ................................ .............................. 91 table 62: 20 - pin, 4.40 mm body, 0.65 mm pitch mechanical data ................................ ........................... 92 table 63: thermal characteristics ................................ ................................ ................................ ............. 94 table 64: document revision history ................................ ................................ ................................ ........ 99
stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 list of figures docid025118 rev 4 7 / 101 list of figures figure 1: block diagram ................................ ................................ ................................ ............................ 10 figure 2: flash memory organization ................................ ................................ ................................ ....... 13 figure 3: stm8af6213/STM8AF6223 tssop20 pinout ................................ ................................ ......... 20 figure 4: STM8AF6223a tssop20 pinout ................................ ................................ .............................. 21 figure 5: stm8af6226 lqfp32 pinout ................................ ................................ ................................ ... 25 figure 6: memory map ................................ ................................ ................................ .............................. 30 figure 7 : pin loading conditions ................................ ................................ ................................ ................ 50 figure 8: pin input voltage ................................ ................................ ................................ ........................ 51 figure 9: fcpumax versus vdd ................................ ................................ ................................ ............... 54 figure 10: external capacitor cext ................................ ................................ ................................ ......... 55 figure 11: typ idd(run) vs. vdd hse user external clock, fcpu = 16 mhz ................................ ........ 63 figure 12: typ idd(run) vs. fcpu hse user external clock, vdd = 5 v ................................ ............... 63 figure 13: typ idd(run) vs. vdd hsi rc osc, fcpu = 16 mhz ................................ ............................ 64 figure 14: typ idd(wfi) vs. vdd hse user external clock, fcpu = 16 mhz ................................ ......... 64 figure 15: typ idd(wfi) vs. fcpu hse user external clock, vdd = 5 v ................................ ................ 64 figure 16: typ idd(wfi) vs. vdd hsi rc osc, fcpu = 16 mhz ................................ ............................. 65 figure 17: hse external clock source ................................ ................................ ................................ ...... 66 figure 18: hse oscillator circuit diagram ................................ ................................ ................................ .. 67 figure 19: typical vil and vih vs vdd @ 4 temperatures ................................ ................................ ..... 7 1 figure 20: typical p ull - up resistance vs vdd @ 4 temperatures ................................ ............................. 71 figure 21: typical pull - up current vs vdd @ 4 temperatures ................................ ................................ .. 72 figure 22: typ. vol @ vdd = 5 v (standard ports) ................................ ................................ ................ 73 figure 23: typ. vol @ vdd = 3.3 v (standard ports) ................................ ................................ ............. 73 figure 24: typ. vol @ vdd = 5 v (true open drain ports) ................................ ................................ ...... 74 figure 25: typ. vol @ vdd = 3.3 v (true open drain ports) ................................ ................................ ... 74 figure 26: typ. vol @ vdd = 5 v (high sink ports) ................................ ................................ ................ 75 figure 27: typ. vol @ vdd = 3.3 v (high sink ports) ................................ ................................ ............. 75 figure 28: typ. vdd - voh@ vdd = 5 v (standard ports) ................................ ................................ ...... 76 figure 29: typ. vdd - voh @ vdd = 3.3 v (standard ports) ................................ ................................ .. 76 figure 30: typ. vdd - voh@ vdd = 5 v (high sink ports) ................................ ................................ ..... 77 figure 31: typ. vdd - voh@ vdd = 3.3 v (high sink ports) ................................ ................................ .. 77 figure 32: typical nrst vil and vih vs vdd @ 4 temperatures ................................ ........................... 78 figure 33: typical nrst pull - up resistance vs vdd @ 4 temperatures ................................ .................. 78 figure 34: typical nrst pull - up current vs vdd @ 4 temperatures ................................ ....................... 79 figure 35: recommended reset pin protection ................................ ................................ ........................ 79 figure 36: spi timing diagram - slave mode and cpha = 0 ................................ ................................ .... 81 figure 37: spi timing diagram - slave mode and cpha = 1 ................................ ................................ .... 81 figure 38: spi timing diagram - master mode(1) ................................ ................................ ..................... 82 figure 39: typical application with i2c bus and timing diagram ................................ .............................. 84 figure 40: adc accuracy characteristics ................................ ................................ ................................ .. 86 figure 41: typic al application with adc ................................ ................................ ................................ ... 87 figure 42: 32 - pin low profile quad flat package (7 x 7) ................................ ................................ ............. 91 figure 43: 20 - pin, 4.40 mm body, 0.65 mm p itch ................................ ................................ ..................... 92 figure 44: ordering information scheme ................................ ................................ ................................ .. 96
introduction stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 8 / 101 docid025118 re v 4 1 introduction this datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information. ? for complete information on the stm8a microcontroller memory, registers and peripherals, please refer to the stm8s and stm8af mi crocontroller family reference manual (rm0016). ? for information on programming, erasing and protection of the internal flash memory please refer to the stm8s and stm8af flash programming manual (pm0051). ? for information on the debug and swim (single wire interface module) refer to the stm8 swim communication protocol and debug module user manual (um0470). ? for information on the stm8 core, please refer to the stm8 cpu programming manual (pm0044).
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 description docid025118 rev 4 9 / 101 2 description the stm8af6213, STM8AF6223, STM8AF6223a and stm8af6226 8 - bit microcontrollers offer 4 to 8 kbytes flash program memory, plus integrated true data eeprom. the stm8s and stm8a microcontroller family reference m anual (rm0016) refers to devices in this family as low - density. they provide the following benefits: performance, robustness, and reduced system cost. device performance and robustness are ensured by advanced core and peripherals made in a state - of - the art technology, a 16 mhz clock frequency, robust i/os, independent watchdogs with separate clock source, and a clock security system. the system cost is reduced thanks to an integrated true data eeprom for up to 300 kwrite/erase cycles and a high system inte gration level with internal clock oscillators, watchdog and brown - out reset. full documentation is offered as well as a wide choice of development tools. table 1: stm8af6226/STM8AF6223/STM8AF6223a/stm8af6213 device stm8af6226 STM8AF6223 STM8AF6223a stm8a f6213 pin count 32 20 max. number of gpios (i/os) 28 including 21 high sink i/o 16 including 12 high sink i/os ext. interrupt pins 28 16 timer capcom channels 6 7 6 7 timer complementary outputs 3 1 2 1 a/d converter channels 7 5 7 5 low densit y flash program memory(bytes) 8k 4k data eeprom (bytes) 640 (1) ram (bytes) 1k peripheral set multipurpose timer (tim1), spi, i2c, , linuart, window wdg, independent wdg, adc, pwm timer (tim5), 8 - bit timer (tim6) notes: (1) no read - while - write (rww) capability.
block diagram stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 10 / 101 docid025118 re v 4 3 block diagram figure 1 : block diagram x t a l 1 - 1 6 m h z r c i n t . 1 6 m h z r c i n t . 1 2 8 k h z s t m 8 c o r e d e b u g / s w i m i 2 c s p i l i n u a r t 1 6 - b i t g e n e r a l p u r p o s e a w u t i m e r r e s e t b l o c k r e s e t p o r b o r c l o c k c o n t r o l l e r d e t e c t o r c l o c k t o p e r i p h e r a l s a n d c o r e 8 m b i t / s l i n a d d r e s s a n d d a t a b u s w i n d o w w d g u p t o 8 k b y t e p r o g r a m f l a s h 6 4 0 b y t e s 1 k b y t e s a d c 1 4 c a p c o m r e s e t 4 0 0 k b i t / s s i n g l e w i r e d e b u g i n t e r f . s p i e m u l . c h a n n e l s 1 6 - b i t a d v a n c e d c o n t r o l t i m e r ( t i m 1 ) 8 - b i t b a s i c t i m e r d a t a e e p r o m r a m u p t o b e e p e r 1 / 2 / 4 k h z b e e p i n d e p e n d e n t w d g ( t i m 6 ) 3 c a p c o m c h a n n e l s u p t o + 3 c o m p l e m e n t a r y o u t p u t s t i m e r ( t i m 5 ) u p t o 7 c h a n n e l s
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 product overview docid025118 rev 4 11 / 101 4 product overview the following section intends to give an overview of the basic features of the device functional modules and peripherals. for more detailed information please refer to the corresponding family reference manual (rm 0016). 4.1 central processing unit stm8 the 8 - bit stm8 core is designed for code efficiency and performance. it contains 6 internal registers which are directly ad dressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions. architecture and registers ? harvard architecture ? 3 - stage pipeline ? 32 - bit wide program memory bus - single cycle fetching for most instructions ? x and y 16 - bit index registers - enabling indexed addressing modes with or without offset and read - modify - write type data manipulations ? 8 - bit accumulator ? 24 - bit program counter - 16 - mbyte linear memory space ? 16 - bit stack pointer - acc ess to a 64 k - level stack ? 8 - bit condition code register - 7 condition flags for the result of the last instruction addressing ? 20 addressing modes ? indexed indirect addressing mode for look - up tables located anywhere in the address space ? stack pointer re lative addressing mode for local variables and parameter passing instruction set ? 80 instructions with 2 - byte average instruction size ? standard data movement and logic/arithmetic functions ? 8 - bit by 8 - bit multiplication ? 16 - bit by 8 - bit and 16 - bit by 16 - b it division ? bit manipulation ? data transfer between stack and accumulator (push/pop) with direct stack access ? data transfer using the x and y registers or direct memory - to - memory transfers
product overview stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 12 / 101 docid025118 re v 4 4.2 single wire interface module (swim) and debug module (dm) the single wire interface module and debug module permits non - intrusive, real - time in - circuit debugging and fast memory programming. swim single wire i nterface module for direct access to the debug module and memory programming. the interface can be activated in all device operation modes. the maximum data transmission speed is 145 bytes/ms. debug module the non - intrusive debugging module features a per formance close to a full - featured emulator. beside memory and peripherals, also cpu operation can be monitored in real - time by means of shadow registers. ? r/w to ram and peripheral registers in real - time ? r/w access to all resources by stalling the cpu ? br eakpoints on all program - memory instructions (software breakpoints) ? two advanced breakpoints, 23 predefined configurations 4.3 interrupt controller ? nested interrupts with three software priority levels ? 32 interrupt vectors with hardware priority ? up to 28 external interrupts on 7 vectors including tli ? trap and reset interrupts 4.4 flash program and data eeprom memory ? up to 8 kbytes of flash program single voltage flash memory ? 640 bytes true data eeprom ? user option byte area write protection (wp) write protection of flash program memory and data eeprom is provided to avoid uni ntentional overwriting of memory that could result from a user software malfunction. there are two levels of write protection. the first level is known as mass (memory access security system). mass is always enabled and protects the main flash program mem ory, data eeprom and option bytes. to perform in - application programming (iap), this write protection can be removed by writing a mass key sequence in a control register. this allows the application to write to data eeprom, modify the contents of main pro gram memory or the device option bytes. a second level of write protection, can be enabled to further protect a specific area of memory known as ubc (user boot code). refer to the figure below. the size of the ubc is programmable through the ubc option b yte, in increments of 1 page (64 - byte block) by programming the ubc option byte in icp mode. this divides the program memory into two areas: ? main program memory: up to 8 kbytes minus ubc
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 product overview docid025118 rev 4 13 / 101 ? user - specific boot code (ubc): configurable up to 8 kbytes the ub c area remains write - protected during in - application programming. this means that the mass keys do not unlock the ubc area. it protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and u sually the iap and communication routines. figure 2 : flash memory organization read - out protection (rop) the read - out protection blocks reading and writing the flash program memory and data eeprom memory in icp mode (and debug m ode). once the read - out protection is activated, any attempt to toggle its status triggers a global erase of the program and data memory. even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection f or a general purpose microcontroller. u b c a r e a r e m a i n s w r i t e p r o t e c t e d d u r i n g i a p p r o g r a m m e m o r y a r e a w r i t e a c c e s s p o s s i b l e f o r i a p d a t a m e m o r y a r e a ( 6 4 0 b y t e s ) o p t i o n b y t e s p r o g r a m m a b l e a r e a ( f r o m 6 4 b y t e ( 1 p a g e ) t o u p t o 8 k b y t e ( i n 1 p a g e s t e p s ) l o w d e n s i t y f l a s h p r o g r a m m e m o r y ( u p t o 8 k b y t e ) d a t a e e p r o m m e m o r y
product overview stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 14 / 101 docid025118 re v 4 4.5 clock controller the clock controller distributes the system clock (f master ) coming from different oscillators to the core and the p eripherals. it also manages clock gating for low power modes and ensures clock robustness. features ? clock prescaler: to get the best compromise between speed and current consumption the clock frequency to the cpu and peripherals can be adjusted by a progr ammable prescaler. ? safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. the clock signal is not switched until the new clock source is ready. the design guarantees glitch - free switching. ? clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. ? master clock sources: four different clock sources can be used to drive the master clock: ? 1 - 16 mhz high - speed external crysta l (hse) ? up to 16 mhz high - speed user - external clock (hse user - ext) ? 16 mhz high - speed internal rc oscillator (hsi) ? 128 khz low - speed internal rc (lsi) ? startup clock: after reset, the microcontroller restarts by default with an internal 2 mhz clock (hsi/ 8). the prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. ? clock security system (css): this feature can be enabled by software. if an hse clock failure occurs, the internal rc (16 mhz/8) is au tomatically selected by the css and an interrupt can optionally be generated. ? configurable main clock output (cco): this outputs an external clock for use by the application. table 2: peripheral clock gating bit assignments in clk_pckenr1/2 registers bi t peripheral clock bit peripheral clock bit peripheral clock bit peripheral clock pcken17 tim1 pcken13 linuart pcken27 reserved cken23 adc pcken16 tim5 pcken12 reserved pcken26 reserved pcken22 awu pcken15 reserved pcken11 spi pcken25 reserved pcken21 reserved pcken14 tim6 pcken10 i 2 c pcken24 reserved pcken20 reserved
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 product overview docid025118 rev 4 15 / 101 4.6 power management for e fficent power management, the application can be put in one of four different low - power modes. you can configure each mode to obtain the best compromise between lowest power consumption, fastest start - up time and available wakeup sources. ? wait mode: in thi s mode, the cpu is stopped, but peripherals are kept running. the wakeup is performed by an internal or external interrupt or reset. ? active halt mode with regulator on: in this mode, the cpu and peripheral clocks are stopped. an internal wakeup is generat ed at programmable intervals by the auto wake up unit (awu). the main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. wakeup is triggered by the internal awu interrupt, external interrupt or reset. ? active halt mode with regulator off: this mode is the same as active halt with regulator on, except that the main voltage regulator is powered off, so the wake up time is slower. ? halt mode: in this mode the microcon troller uses the least power. the cpu and peripheral clocks are stopped, the main voltage regulator is powered off. wakeup is triggered by external event or reset. 4.7 watchdog timers the watchdog system is based on two independent timers providing maximum security to the applications. activation of the watchdog timers is controlled by option bytes or by software. once activated, the watchdogs cannot be disabled by the user prog ram without performing a reset. window watchdog timer the window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. the window function can be used to trim the watchdog behavior to match the application perfectly. the application software must refresh the counter before time - out and during a limited time window. a reset is generated in two situa tions: 1. timeout: at 16 mhz cpu clock the time - out period can be adjusted between 75 s up to 64 ms. 2. refresh out of window: the downcounter is refreshed before its value is lower than the one stored in the window register. independent watchdog timer the i ndependent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. it is clocked by the 128 khz lsi internal rc clock source, and thus stays active even in case of a cpu clock failure the iwdg time base spa ns from 60 s to 1 s.
product overview stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 16 / 101 docid025118 re v 4 4.8 auto wakeup counter ? used for auto wakeup from active halt mode ? clock source: internal 128 khz internal low frequency rc oscillator or external clo ck ? lsi clock can be internally connected to tim1 input capture channel 1 for calibration 4.9 beeper the beeper function outputs a signal on the beep pin for sound generation. the signal is in the range of 1, 2 or 4 khz. the beeper output port is only available through the alternate function remap option bit afr7. 4.10 tim1 - 16 - bit advanced control timer this is a high - end timer designed for a wide range of control applications. with its complementary outputs, dead - time control and center - aligned pwm capability, the field of applications is extended to motor control, lighting and half - bridge driver ? 16 - bit up, down and up/down autoreload counter with 16 - bit prescaler ? four independent capture/compare channels (capcom) configurable as input capture, output compare, pwm generation (edge and center aligned mode) and single pulse mode output ? sync hronization module to control the timer with external signals or to synchronise with tim5 or tim6 ? break input to force the timer outputs into a defined state ? three complementary outputs with adjustable dead time ? encoder mode ? interrupt sources: 3 x inpu t capture/output compare, 1 x overflow/update, 1 x break 4.11 tim5 - 16 - bit general purpose timer ? 16 - bit autoreload (ar) up - counter ? 15 - bit prescaler adjustable to fixed power of 2 ratios 132768 ? 3 individually configurable capture/compare channels ? pwm mode ? interrupt sources: 3 x input capture/output compare, 1 x overflow/update ? synchronization module to control the timer with external signals or to synchroni ze with tim1 or tim6
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 product overview docid025118 rev 4 17 / 101 4.12 tim6 - 8 - bit basic timer ? 8 - bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128 ? clock source: cpu clock ? interrupt sourc e: 1 x overflow/update ? synchronization module to control the timer with external signals or to synchronize with tim1 or tim5. table 3: tim timer features timer counter size (bits) prescaler counting mode capcom channels complementary outputs ext . trigger timer synchronization/ chaining tim1 16 any integer from 1 to 65536 up/down 4 3 yes yes tim5 16 any power of 2 from 1 to 32768 up 3 0 no tim6 8 any power of 2 from 1 to 128 up 0 0 no 4.13 analog - to - digital converter (adc1) the stm8af6213/STM8AF6223, STM8AF6223a and stm8af6226 products contain a 10 - bit successive approximation a/d converter (adc1) with up to 7 external and 1 internal multiplexed input channels and the following main features: ? input voltage range: 0 to v dd ? input voltage range: 0 to v dda ? conversion time: 14 clock cycles ? single and continuous and buffered continuous conversion modes ? buff er size (n x 10 bits) where n = number of input channels ? scan mode for single and continuous conversion of a sequence of channels ? analog watchdog capability with programmable upper and lower thresholds ? internal reference voltage on channel ain7 ? analog watchdog interrupt ? external trigger input ? trigger from tim1 trgo ? end of conversion (eoc) interrupt additional ain12 analog input is not selectable in adc scan mode or with analog watchdog. values converted from ain12 are stored only into the adc_drh /adc_drl registers.
product overview stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 18 / 101 docid025118 re v 4 internal bandgap reference voltage channel ain7 is internally connected to the internal bandgap reference voltage. the internal bandgap reference is constant and can be used, for example, to monitor v dd . it is independent of variatio ns in v dd and ambient temperature t a . 4.14 communication interfaces the following communication interfaces are implemented: ? linuart: full feature uart, synchronous mode , spi master mode, smartcard mode, irda mode, single wire mode, lin2.1 capability ? spi : full and half - duplex, 8 mbit/s ? i2c: up to 400 kbit/s some peripheral names differ between the datasheet and the stm8a/s reference manual (see table 4: "communication peripheral naming correspondence" ). table 4: communication peripheral naming correspondence peripheral name in datasheet peripheral name in reference manual (rm0016) linuart uart4 4.14.1 linuart main features ? one mbit/s full duplex sci ? spi emulation ? high precision baud rate generator ? smartcard emulation ? irda sir encoder decoder ? lin mode ? single wire half duplex mode lin mode ? master mode ? lin br eak and delimiter generation ? lin break and delimiter detection with separate flag and interrupt source for read back checking. ? slave mode ? autonomous header handling C one single interrupt per valid head ? mute mode to filter responses ? identifier parity error checking ? lin automatic resynchronization, allowing operation with internal rc oscillator (hsi) clock source ? break detection at any time, even during a byte reception ? header errors detection: ? delimiter too short ? synch field error ? deviation error (if automatic resynchronization is enabled)
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 product overview docid025118 rev 4 19 / 101 ? framing error in synch field or identifier field ? header time - out asynchronous communication (uart mode) ? full duplex communication - nrz standard format (mark/space) ? programmable transmit and receive baud rat es up to 1 mbit/s (f cpu /16) and capable of following any standard baud rate regardless of the input frequency ? separate enable bits for transmitter and receiver ? two receiver wakeup modes: ? address bit (msb) ? idle line (interrupt) ? transmission error detec tion with interrupt generation ? parity control synchronous communication ? full duplex synchronous transfers ? spi master operation ? 8 - bit data communication ? maximum speed: 1 mbit/s at 16 mhz (f cpu /16) 4.14.2 spi ? maximum speed: 8 mbit/s (f master /2) both for master and slave ? full duplex synchronous transfers ? simplex synchronous transfers on two lines with a possible bidirectional data line ? master or slave operation - selectable by hardware or software ? crc calculation ? 1 byte tx and rx buffer ? slave/master selection input pin 4.14.3 i2c ? i2c master features: ? clock generation ? start and stop generation ? i2c slave features: ? programm able i2c address detection ? stop bit detection ? generation and detection of 7 - bit/10 - bit addressing and general call ? supports different communication speeds: ? standard speed (up to 100 khz) ? fast speed (up to 400 khz)
pinout and pin description stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 20 / 101 docid025118 re v 4 5 pinout and pin description table 5: legend/abbreviations for pinout tables type i= input, o = output, s = power supply level input cm = cmos output hs = high sink output speed o1 = slow ( up to 2 mhz) o2 = fast (up to 10 mhz) o3 = fast/slow programmability with slow as default state after reset o4 = fast/slow programmability with fast as default state after reset port and control configuration input float = floating, wpu = weak pul l - up output t = true open drain, od = open drain, pp = push pull reset state bold x (pin state after internal reset release). unless otherwise specified, the pin state is the same during the reset phase and after the internal reset release. 5.1 st m8af6213/STM8AF6223 tssop20 pinout figure 3 : stm8af6213/STM8AF6223 tssop20 pinout 1. (hs) high sink capability. 2. (t) true open drain (p - buf fer and protection diode to v dd not implemented). 3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 8 1 2 3 4 5 6 7 9 10 20 19 18 17 16 15 14 13 12 11 pd3 (hs)/ain4/tim5_ch2/adc_etr [linuart_ck] tim5_ch1/beep/(hs) pd4 ain5/linuart_tx/(hs) pd5 ain6/linuart_rx/(hs) pd6 nrst oscin/pa1 oscout/pa2 vss vcap vdd [spi_nss] tim5_ch3/(hs) pa3 pb4 (t)/i2c_scl [adc_etr] pc3 (hs)/tim1_ch3 [tli][tim1_ch1n] pc4 (hs)/tim1_ch4/clk_cco/ain2 [tim1_ch2n] pc5 (hs)/spi_sck [tim5_ch1] pc6 (hs)/spi_mosi [tim1_ch1] pc7 (hs)/spi_miso [tim1_ch2] pd1 (hs)/swim pd2 (hs)/ain3 [tim5_ch3] pb5 (t)/i2c_sda [tim1_bkin]
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 pinout and pin description docid025118 rev 4 21 / 101 5.2 STM8AF6223pxax tssop20 pinout figure 4 : STM8AF6223a tssop20 pinout 1. (hs) high sink capability. 2. (t) true open drain (p - buffer and protection diode to v dd not implemented). 3. [ ] alterna te function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 5.3 tssop20 pin description table 6: stm8af6213/STM8AF6223 tssop20 pin description tssop pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] floating wpu ext. interrupt high sink (1) speed od pp 4 nrst i/o x reset 5 pa1/ oscin (2) i/o x x x o1 x x port a1 resonator/ crystal in 6 pa2/ oscout i/o x x x o1 x x port a2 resonator/ crystal out 7 v ss s digital ground 8 vcap s 1.8 v regulator capacitor 9 v dd s digital power supply 10 pa3/ tim5_ch3 [spi_nss] i/o x x x hs o3 x x port a 3 timer 5 channel 3 spi master/ slave select [afr1] 11 pb5/ i2c_sda [tim1_bkin] i/o x x o1 t (3) port b5 i 2 c data timer 1 - break input [afr4] 12 pb4/ i2c_scl [adc_etr] i/o x x o1 t (3) port b4 i 2 c clock adc external trigger [afr4] 8 1 2 3 4 5 6 7 9 10 20 19 18 17 16 15 14 13 12 1 1 pd3 (hs)/ain4/tim5_ch2/adc_etr [linua r t_ck] tim5_ch1/beep/spi_nss/(hs) pd4 ain5/linua r t_tx/(hs) pd5 ain6/linua r t_rx/(hs) pd6 nrs t oscin/ p a1 oscout/ p a2 vss vca p vdd [tim1_bkin] i2c_sda/(t) pb5 pb1 (hs)/tim1_ch2n/ain1 pb0 (hs)/tim1_ch1n/ain0 pc4 (hs)/tim1_ch4/clk_cco/ain2 [tim1_ch2n] pc5 (hs)/spi_sck [tim5_ch1] pc6 (hs)/spi_mosi [tim1_ch1] pc7 (hs)/spi_miso [tim1_ch2] pd1 (hs)/swim pd2 (hs)/ain3/tli [tim5_ch3] pb4 (t)/i2c_sc l [adc_etr]
pinout and pin description stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 22 / 101 docid025118 re v 4 tssop pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] floating wpu ext. interrupt high sink (1) speed od pp 13 pc3/ tim1_ch3/[tli]/[tim1_ch1n ] i/o x x x hs o3 x x port c3 timer 1 - channel 3 top level interrupt [afr3] timer 1 inverted channel 1 [afr7] 14 pc4/ tim1_ch4/ clk_cco/ain2/[tim1_ch2n] i/o x x x hs o3 x x port c4 timer 1 - channel 4 /configurable clock output analog input 2 [afr2]timer 1 inverted channel 2 [afr7] 15 pc5/spi_sck [tim5_ch1] i/o x x x hs o3 x x port c5 spi clock timer 5 channel 1 [afr0] 16 pc6/ spi_mosi [tim1_ch1] i/o x x x hs o3 x x port c6 pi master out/slave in timer 1 channel 1 [afr0] 17 pc7/ spi_miso [tim1_ch2] i/o x x x hs o3 x x port c7 spi master in/ slave out timer 1 channel 2[afr0] 18 pd1/ swim (4) i/o x x x hs o4 x x port d1 swim data interface 19 pd2/ain3 [tim5_ch3] i/o x x x hs o3 x x port d2 analog i nput 3 [afr2] timer 52 - channel 3 [afr1] 20 pd3/ ain4/ tim5_ch2/ adc_etr i/o x x x hs o3 x x port d3 analog input 4 timer 52 - channel 2/adc external trigger 1 pd4/ tim5_ch1/ beep [linuart_ck] i/o x x x hs o3 x x port d4 timer 5 - channel 1/beep output linuart clock [afr2] 2 pd5/ ain5/ linuart_tx i/o x x x hs o3 x x port d5 analog input 5/ linuart data transmit 3 pd6/ ain6/ linuart_rx i/o x x x hs o3 x x port d6 ana log input 6/ linuart data receive notes: (1) i/o pins used simultaneously for high current source/sink must be uniformly spaced around the package. in addition, the total driven current must respect the absolute maximum ratings ( see section "absolute m aximum ratings").
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 pinout and pin description docid025118 rev 4 23 / 101 (2) when the mcu is in halt/active - halt mode, pa1 is automatically configured in input weak pull - up and cannot be used for waking up the device. in this mode, the output state of pa1 is not driven. it is recommended to use pa1 only in inp ut mode if halt/active - halt is used in the application. (3) in the open - drain output column, t defines a true open - drain i/o (p - buffer, weak pull - up, and protection diode to vdd are not implemented) (4) the pd1 pin is in input pull - up during the reset ph ase and after internal reset release. table 7: STM8AF6223a tssop20 pin description tssop pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] floating wpu ext. interrupt high sink (1) speed od pp 4 nrst i/o x reset 5 pa1/ oscin (2) i/o x x x o1 x x port a1 resonator/ crystal in 6 pa2/ oscout i/o x x x o1 x x port a2 resonator/ crystal out 7 v ss s digital ground 8 vcap s 1.8 v regulator capacitor 9 v dd s digital power supply 10 pb5/ i2c_sda [tim1_bkin] i/o x x x o1 t (3) x port a5 i 2 c data timer 1 - break input [afr4] 11 pb4/ i2c_scl [adc_etr] i/o x x o1 t (3) port b4 i 2 c clock adc external trigger [afr4] 12 pb1/ tim1_ch2n/ ain1 i/o x x x hs o3 x x port b1 timer 1 - inverted channel 2/analog input 1 13 pb0/ tim1_ch1n/ain0 i/o x x x hs o3 x x port b0 timer 1 - inverted channel 1/analog input 0 14 pc4/ tim1_ch4/ clk_cco/ain2/[tim1_ch2] i/o x x x hs o3 x x port c4 timer 1 - channel 4 /configurable clock output analog input 2 [afr2]timer 1 channel 2 [afr7] 15 pc5/spi_sck [tim5_ch1] i/o x x x hs o3 x x port c5 spi clock timer 5 channel 1 [afr0] 16 pc6/ spi_mosi [tim1_ch1] i/o x x x hs o3 x x port c6 pi master out/slave in timer 1 channel 1 [afr0] 17 pc7/ spi_miso [tim1_ch2] i/o x x x hs o3 x x port c7 spi master in/ slave out timer 1 channel 2[afr0]
pinout and pin descript ion stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 24 / 101 docid025118 re v 4 tssop pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] floating wpu ext. interrupt high sink (1) speed od pp 18 pd1/ swim (4) i/o x x x hs o4 x x port d1 swim data interface 19 pd2/ain3/ tli[tim5_ch3] i/o x x x hs o3 x x port d2 analog input 3 [afr2] timer 5 - channel 3 [afr1] 20 p d3/ ain4/ tim5_ch2/ adc_etr i/o x x x hs o3 x x port d3 analog input 4 timer 52 - channel 2/adc external trigger 1 pd4/ tim5_ch1/ beep/spi_nss [linuart_ck] i/o x x x hs o3 x x port d4 timer 5 - channel 1/beep output linuart clock [afr2] 2 pd5/ ain5/ linuart_tx i/o x x x hs o3 x x port d5 analog input 5/ linuart data transmit 3 pd6/ ain6/ linuart_rx i/o x x x hs o3 x x port d6 analog input 6/ linuart data receive note s: (1) i/o pins used simultaneously for high current source/sink must be uniformly spaced around the package. in addition, the total driven current must respect the absolute maximum ratings ( see section "absolute maximum ratings"). (2) when the mcu is in h alt/active - halt mode, pa1 is automatically configured in input weak pull - up and cannot be used for waking up the device. in this mode, the output state of pa1 is not driven. it is recommended to use pa1 only in input mode if halt/active - halt is used in the application. (3) in the open - drain output column, t defines a true open - drain i/o (p - buffer, weak pull - up, and protection diode to vdd are not implemented) (4) the pd1 pin is in input pull - up during the reset phase and after internal reset release.
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 pinout and pin description docid025118 rev 4 25 / 101 5.4 stm8af6226 lqfp32 pinout figure 5 : stm8af6226 lqfp32 pinout 1. (hs) high sink capability. 2. (t) true open drain (p - buffer and protection diode to v dd not implemented). 3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). [adc_etr] ic_scl/(t)pb4 tim1_etr/ain3/(hs) pb3 tim1_ch3n/ain2/(hs)pb2 tim1_ch2n/ain1/(hs) pb1 tim1_ch1n/ain0/(hs) pb0 pb7 pb6 [tim1_bkin]i2c_sda/(t)pb5 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 vcap vdd [linuart_tx][spi_nss] tim5_ch3/(hs) pa3 [linuart_rx] pf4 nrst oscin/pa1 oscout/pa2 vss pc3(hs)/tim1_ch3 [tli] [tim1_ch1n] pc2(hs)/tim1_ch2 [tim1_ch3n] pc1(hs)/tim1_ch1/linuart_ck[tim1_ch2n] pe5/spi_nss [tim1_ch1n] pc7 (hs)/spi_miso [tim1_ch2] pc6 (hs)/spi_mosi [tim1_ch1] pc5 (hs)/spi_sck [tim5_ch1] pc4(hs)tim1_ch4/clk_cco [ain2] [tim1_ch2n] pd3 (hs)/ain4/tim5_ch2/adc_etr pd2 (hs)[ain3] [tim5_ch3] pd1 (hs)/swim pd0 (hs)/ tim1_bkin [clk_cco] pd7 (hs)/tli [tim1_ch4] pd6 (hs)/ain6/linuart_rx pd5 (hs)/ain5/linuart_tx pd4 (hs)/beep/tim5_ch1[linuart_ck]
pinout and pin description stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 26 / 101 docid025118 re v 4 5.5 lqfp32 pin description table 8: lqfp32 pin description lqfp32 pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] floating wpu ext. interrupt high sink (1) speed od pp 1 nrst i/o x reset 2 pa1/ oscin (2) i/o x x x o1 x x port a1 resonator/ crystal in 3 pa2/ oscout i/o x x x o1 x x port a2 resonator/ crystal out 4 v ss s digital ground 5 vcap s 1.8 v regulator capacitor 6 v dd s digital power supply 7 pa3/ tim5_ch3 [spi_nss] [linuart_tx] i/ o x x x hs o3 x x port a3 timer 52 channel 3 spi master/ slave select [afr1]/ linuart data transmit [afr1:0] 8 pf4 [linuart_rx] i/o x x o1 x x port f4 linuart data receive [afr1:0] 9 pb7 i/o x x x o1 x x port b7 10 pb6 i/o x x x o1 x x port b6 11 pb5/ i2c_sda [tim1_bkin] i/o x x o1 t (3) port b5 i 2 c data timer 1 - break input [afr4] 12 pb4/ i2c_scl [adc_etr] i/o x x o1 t (3) port b4 i 2 c clock adc external trigger [afr4] 13 pb3/ ain3/tim1_etr i/o x x x hs o3 x x port b3 analog input 3/ timer 1 external trigger 14 pb2/ ain2/ tim1_ch3n i/o x x x hs o3 x x port b2 analog input 2/ timer 1 - inverted channel 3
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 pinout and pin description docid025118 rev 4 27 / 101 lqfp32 pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] floating wpu ext. interrupt high sink (1) speed od pp 15 pb1/ ain1/ tim1_ch2n i/o x x x hs o3 x x port b1 analog input 1/ timer 1 - inverted channel 2 16 pb0/ ain0/ tim1_ch1n i/o x x x hs o3 x x port b0 analog input 0/ timer 1 - inverted channel 1 17 pe5/ spi_nss [tim1_ch1n] i/o x x x hs o3 x x port e5 spi master/ slave select timer 1 - inverted channel 1 [afr1:0] 18 pc1/ tim1_ch1/ linuart_ck [tim1_ch2n] i/o x x x hs o3 x x port c1 timer 1 - channel 1 linuart clock timer 1 - inverted channel 2 [afr1:0] 19 pc2/ tim1_ch2 [tim1_ch3n] i/o x x x hs o3 x x port c2 timer 1 - channel 2 timer 1 - inverted channel 3 [afr1:0] 20 pc3/ tim1_ch3/[tli][tim1_ch1n ] i/o x x x hs o3 x x port c3 timer 1 - channel 3 top level interrupt [afr3] timer 1 inverted channel 1 [afr7] 21 pc4/ tim1_ch4/ clk_cco/[ain2][tim1_ch2n] i/o x x x hs o3 x x port c4 timer 1 - channel 4 /configurable clock output analog input 2 [afr2]timer 1 inverted channel 2 [afr7] 22 pc5/spi_sck [tim5_ch1] i/o x x x hs o3 x x port c5 spi clock timer 5 channel 1 [afr0] 23 pc6/ spi_mosi [tim1_ch1] i /o x x x hs o3 x x port c6 pi master out/slave in timer 1 channel 1 [afr0] 24 pc7/ spi_miso [tim1_ch2] i/o x x x hs o3 x x port c7 spi master in/ slave out timer 1 channel 2[afr0] 25 pd0/ tim1_bkin [clk_cco] i/o x x x hs o3 x x port d0 timer 1 - break input configurable clock output [afr5]
pinout and pin description stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 28 / 101 docid025118 re v 4 lqfp32 pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] floating wpu ext. interrupt high sink (1) speed od pp 26 pd1/ swim (4) i/o x x x hs o4 x x port d1 swim data interface 27 pd2/[ain3] [tim5_ch3] i/o x x x hs o3 x x port d2 analog input 3 [afr2] timer 52 - channel 3 [afr1] 28 pd3/ ain4/ tim5_ch2/ adc_etr i/o x x x hs o3 x x port d3 analog input 4 timer 52 - channel 2/adc external trigger 29 pd4/ tim5_ ch1/ beep [linuart_ck] i/o x x x hs o3 x x port d4 timer 5 - channel 1/beep output linuart clock [afr2] 30 pd5/ ain5/ linuart_tx i/o x x x hs o3 x x port d5 analog input 5/ linuart data transmit 31 pd6/ ain6 / linuart_rx i/o x x x hs o3 x x port d6 analog input 6/ linuart data receive 32 pd7/ tli [tim1_ch4] i/o x x x hs o3 x x port d7 top level interrupt timer 1 - channel 4 [afr6] notes: (1) i/o pins used simultane ously for high current source/sink must be uniformly spaced around the package. in addition, the total driven current must re spect the absolute maximum ratings ( see section "absolute maximum ratings"). (2) when the mcu is in halt/active - halt mode, pa1 is automatically configured in input weak pull - up and cannot be used for waking up the device. in this mode, the output state of pa1 is not driven. it is recommended to use pa1 only in input mode if halt/active - halt is used in the application. (3) in the open - drain output column, t defines a true open - drain i/o (p - buffer, weak pull - up, and protection diode to vdd are not implemented) (4) the pd1 pin is in input pull - up during the reset phase and after internal reset release.
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 pinout and pin description docid025118 rev 4 29 / 101 5.6 alternate function remappin g as shown in the rightmost column of the pin description table, some alternate functions can be remapped at different i/o ports by programming one of eight afr (alternate function remap) option bits. when the remapping option is active, the default alternate function is no longer available. to use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. alternate function remapping does not affect gpio capabilities of the i/o ports (see the gpio section of the family reference manual, rm0016).
memory and register map stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 30 / 101 docid025118 re v 4 6 memory and register map 6.1 memory map figure 6 : memory map
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 memory and register map docid025118 rev 4 31 / 101 table 9: memory model for the device covered in this datasheet flash program memory size flash program memory end address ram size ram end address stack roll - over address 8k 0x009fff 1 0x00 03ff 0x00 0200 4k 0x008fff 1 0x00 03ff 0x00 0200 6.2 register map 6.2.1 i/o port hardware register map table 10: i/o port hardware register map address block register label register name reset status 0x00 5000 port a pa_odr port a data output latch register 0x00 0x00 5001 pa_idr port a input pin value register 0xxx (1) 0x00 5002 pa_ddr port a data direction register 0x00 0x00 5003 pa_cr1 port a control register 1 0x00 0x00 5004 pa_cr2 port a control register 2 0x00 0x00 5005 port b pb_odr port b data output latch register 0x00 0x00 5006 pb_idr port b input pin value register 0xxx (1) 0x00 5007 pb_ddr port b data direction register 0x00 0x00 5008 pb_cr1 port b control register 1 0x00 0x00 5009 pb_cr2 port b control register 2 0x00 0x00 500a port c pc_odr port c data output latch register 0x00 0x00 500b pb_idr port c input pin value register 0xxx (1) 0x00 500c pc_ddr port c data direction register 0x00 0x00 500d pc_cr1 port c control register 1 0x00 0x00 500e pc_cr2 port c control register 2 0x00 0x00 500f port d pd_odr port d data output latch register 0x00 0x00 5010 pd_idr port d input pin value register 0xxx (1) 0x00 5011 pd_ddr port d data direction register 0x00 0x00 5012 pd_cr1 port d control register 1 0x02 0x00 5013 pd_cr2 port d control register 2 0x00 0x00 5014 port e pe_odr port e data output latch register 0x00 0x00 5015 pe_idr port e input pin value register 0xxx (1) 0x00 5016 pe_dd r port e data direction register 0x00 0x00 5017 pe_cr1 port e control register 1 0x00 0x00 5018 port e pe_cr2 port e control register 2 0x00
memory and register map stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 32 / 101 docid025118 re v 4 address block register label register name reset status 0x00 5019 port f pf_odr port f data output latch register 0x00 0x00 501a p f_idr port f input pin value register 0xxx (1) 0x00 501b pf_ddr port f data direction register 0x00 0x00 501c pf_cr1 port f control register 1 0x00 0x00 501d pf_cr2 port f control register 2 0x00 notes: (1) depends on the external circuitry. 6.2.2 general hardware register map table 11: general hardware register map address block register lab el register name reset status 0x00 501e to 0x00 5059 reserved area (60 bytes) 0x00 505a flash flash_cr1 flash control register 1 0x00 0x00 505b flash_cr2 flash control register 2 0x00 0x00 505c flash_ncr2 flash complementar y control register 2 0xff 0x00 505d flash _fpr flash protection register 0x00 0x00 505e flash _nfpr flash complementary protection register 0xff 0x00 505f flash _iapsr flash in - application programming status register 0x00 0x0 0 5060 to 0x00 5061 reserved area (2 bytes) 0x00 5062 flash flash _pukr flash program memory unprotection register 0x00 0x00 5063 reserved area (1 byte) 0x00 5064 flash flash _dukr data eeprom unprotection register 0x00 0x00 5065 to 0x00 509f reserved area (59 bytes) 0x00 50a0 itc exti_cr1 external interrupt control register 1 0x00 0x00 50a1 exti_cr2 external interrupt control register 2 0x00 0x00 50a2 to 0x00 50b2 reserved area (17 bytes) 0x00 50b3 rst rst_sr reset status register 0xxx (1) 0x00 50b4 to 0x00 50bf reserved area (12 bytes) 0x00 50c0 clk clk_ickr internal clock control register 0x01
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 memory and register map docid025118 rev 4 33 / 101 address block register lab el register name reset status 0x00 50c1 clk_eckr external clock control registe r 0x00 0x00 50c2 reserved area (1 byte) 0x00 50c3 clk clk_cmsr clock master status register 0xe1 0x00 50c4 clk_swr clock master switch register 0xe1 0x00 50c5 clk_swcr clock switch control register 0xxx 0x00 50c6 clk_ ckdivr clock divider register 0x18 0x00 50c7 clk_pckenr1 peripheral clock gating register 1 0xff 0x00 50c8 clk_cssr clock security system register 0x00 0x00 50c9 clk_ccor configurable clock control register 0x00 0x00 50ca clk_pckenr2 peripheral clock gating register 2 0xff 0x00 50cc clk_hsitrimr hsi clock calibration trimming register 0x00 0x00 50cd clk_swimccr swim clock control register 0bxxxx xxx0 0x00 50ce to 0x00 50d0 reserved area (3 bytes) 0x00 50d1 wwdg wwdg_cr wwdg control register 0x7f 0x00 50d2 wwdg_wr wwdr window register 0x7f 0x00 50d3 to 00 50df reserved area (13 bytes) 0x00 50e0 iwdg iwdg_kr iwdg key register 0xxx (2) 0x00 50e1 iwdg_pr iwdg prescaler register 0x00 0x00 50e2 iwdg_rlr iwdg reload register 0xff 0x00 50e3 to 0x00 50ef reserved area (13 bytes) 0x00 50f0 awu awu_csr1 awu control/status register 1 0x00 0x00 50f1 awu_apr a wu asynchronous prescaler buffer register 0x3f 0x00 50f2 awu_tbr awu timebase selection register 0x00 0x00 50f3 beep beep_csr beep control/status register 0x1f 0x00 50f4 to 0x00 50ff reserved area (12 bytes) 0x00 5200 spi spi_ cr1 spi control register 1 0x00 0x00 5201 spi_cr2 spi control register 2 0x00 0x00 5202 spi_icr spi interrupt control register 0x00
memory and register map stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 34 / 101 docid025118 re v 4 address block register lab el register name reset status 0x00 5203 spi_sr spi status register 0x02 0x00 5204 spi_dr spi data register 0x00 0x00 5205 spi_crcpr spi crc polynomial register 0x07 0x00 5206 spi_rxcrcr spi rx crc register 0xff 0x00 5207 spi_txcrcr spi tx crc register 0xff 0x00 5208 to 0x00 520f reserved area (8 bytes) 0x00 5210 i 2 c i2c_cr1 i 2 c co ntrol register 1 0x00 0x00 5211 i2c_cr2 i 2 c control register 2 0x00 0x00 5212 i2c_freqr i 2 c frequency register 0x00 0x00 5213 i2c_oarl i 2 c own address register low 0x00 0x00 5214 i2c_oarh i 2 c own address register high 0x00 0x00 5215 reserved 0x00 5216 i2c_dr i 2 c data register 0x00 0x00 5217 i2c_sr1 i 2 c status register 1 0x00 0x00 5218 i2c_sr2 i 2 c status register 2 0x00 0x00 5219 i2c_sr3 i 2 c status register 3 0x0x 0x00 521a i 2c_itr i 2 c interrupt control register 0x00 0x00 521b i2c_ccrl i 2 c clock control register low 0x00 0x00 521c i2c_ccrh i 2 c clock control register high 0x00 0x00 521d i2c_triser i 2 c trise register 0x02 0x00 521e i2c_pecr i 2 c packet error checking register 0x00 0x00 521f to 0x00 522f reserved area (17 bytes) 0x00 5230 linuart linuart_sr linuart status register 0xc0 0x00 5231 linuart_dr linuart data register 0xxx 0x00 5232 linuart_brr1 linuart baud rate register 1 0x00 0x00 5233 linuart_brr2 linuart baud rate register 2 0x00 0x00 5234 linuart_cr1 linuart control register 1 0x00 0x00 5235 linuart_cr2 linuart control register 2 0x00 0x00 5236 linuart_cr3 linuart control register 3 0x00 0x00 5237 linuart_cr4 linuart control register 4 0x00
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 memory and register map docid025118 rev 4 35 / 101 address block register lab el register name reset status 0x00 5238 linuart_cr5 linuart control register 5 0x00 0x00 5239 linuart_cr6 linuart control register 6 0x00 0x00 523a linuart_gtr linuart guard time register 0x00 0x00 523b linuart_pscr linuart precaler register 0x00 0x00 523c to 0x00 523f reserved area (20 bytes) 0x00 5250 tim1 tim1_cr1 tim1 control register 1 0x00 0x00 5251 tim1_cr2 tim1 control register 2 0x00 0 x00 5252 tim1_smcr tim1 slave mode control register 0x00 0x00 5253 tim1_etr tim1 external trigger register 0x00 0x00 5254 tim1_ier tim1 interrupt enable register 0x00 0x00 5255 tim1_sr1 tim1 status register 1 0x00 0x00 5 256 tim1_sr2 tim1 status register 2 0x00 0x00 5257 tim1_egr tim1 event generation register 0x00 0x00 5258 tim1_ccmr1 tim1 capture/compare mode register 1 0x00 0x00 5259 tim1_ccmr2 tim1 capture/compare mode register 2 0x00 0x00 525a tim1_ccmr3 tim1 capture/compare mode register 3 0x00 0x00 525b tim1_ccmr4 tim1 capture/compare mode register 4 0x00 0x00 525c tim1_ccer1 tim1 capture/compare enable register 1 0x00 0x00 525d tim1_ccer2 tim1 capture /compare enable register 2 0x00 0x00 525e tim1_cntrh tim1 counter high 0x00 0x00 525f tim1_cntrl tim1 counter low 0x00 0x00 5260 tim1_pscrh tim1 prescaler register high 0x00 0x00 5261 tim1_pscrl tim1 prescaler register l ow 0x00 0x00 5262 tim1_arrh tim1 auto - reload register high 0xff 0x00 5263 tim1_arrl tim1 auto - reload register low 0xff 0x00 5264 tim1_rcr tim1 repetition counter register 0x00 0x00 5265 tim1_ccr1h tim1 capture/compare re gister 1 high 0x00
memory and register map stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 36 / 101 docid025118 re v 4 address block register lab el register name reset status 0x00 5266 tim1_ccr1l tim1 capture/compare register 1 low 0x00 0x00 5267 tim1_ccr2h tim1 capture/compare register 2 high 0x00 0x00 5268 tim1_ccr2l tim1 capture/compare register 2 low 0x00 0x00 5269 tim1_c cr3h tim1 capture/compare register 3 high 0x00 0x00 526a tim1_ccr3l tim1 capture/compare register 3 low 0x00 0x00 526b tim1_ccr4h tim1 capture/compare register 4 high 0x00 0x00 526c tim1_ccr4l tim1 capture/compare register 4 lo w 0x00 0x00 526d tim1_bkr tim1 break register 0x00 0x00 526e tim1_dtr tim1 dead - time register 0x00 0x00 526f tim1_oisr tim1 output idle state register 0x00 0x00 5270 to 0x00 52ff reserved area (147 bytes) 0x00 5300 tim5 tim5_cr1 tim5 control register 1 0x00 0x00 5301 tim5_cr2 tim5 control register 2 0x00 0x00 5302 tim5_smcr tim5 slave mode control register 0x00 0x00 5303 tim5_ier tim5 interrupt enable register 0x00 0x00 5304 tim5_sr1 tim5 status register 1 0x00 0x00 5305 tim5_sr2 tim5 status register 2 0x00 0x00 5306 tim5_egr tim5 event generation register 0x00 0x00 5307 tim5_ccmr1 tim5 capture/compare mode register 1 0x00 0x00 5308 tim5_ccmr2 tim5 capture/compare mode register 2 0x00 0x00 5309 tim5_ccmr3 tim5 capture/compare mode register 3 0x00 0x00 530a tim5_ccer1 tim5 capture/compare enable register 1 0x00 0x00 530b tim5_ccer2 tim5 capture/compare enable register 2 0x0 0 00 530c0x tim5_cntrh tim5 counter high 0x00 0x00 530d tim5_cntrl tim5 counter low 0x00
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 memory and register map docid025118 rev 4 37 / 101 address block register lab el register name reset status 0x00 530e tim5_pscr tim5 prescaler register 0x00 0x00 530f tim5_arrh tim5 auto - reload register high 0xff 0x00 5310 tim5_arrl tim5 auto - reload register low 0xff 0x00 5311 tim5_ccr1h tim5 capture/compare register 1 high 0x00 0x00 5312 tim5_ccr1l tim5 capture/compare register 1 low 0x00 0x00 5313 tim5_ccr2h tim5 capture/compare register 2 high 0x00 0 x00 5314 tim5_ccr2l tim5 capture/compare register 2 low 0x00 0x00 5315 tim5_ccr3h tim5 capture/compare register 3 high 0x00 0x00 5316 tim5_ccr3l tim5 capture/compare register 3 low 0x00 0x00 5317 to 0x00 533f reserved area (43 b ytes) 0x00 5340 tim6 tim6_cr1 tim6 control register 1 0x00 0x00 5341 tim6_cr2 tim6 control register 2 0x00 0x00 5342 tim6_smcr tim6 slave mode control register 0x00 0x00 5343 tim6_ier tim6 interrupt enable register 0x00 0x00 5344 tim6_sr tim6 status register 0x00 0x00 5345 tim6_egr tim6 event generation register 0x00 0x00 5346 tim6_cntr tim6 counter 0x00 0x00 5347 tim6_pscr tim6 prescaler register 0x00 0x00 5348 tim6_arr tim6 au to - reload register 0xff 0x00 5349 to 0x00 53df reserved area (153 bytes) 0x00 53e0 to 0x00 53f3 adc1 adc _dbxr adc data buffer registers 0x00 0x00 53f4 to 0x00 53ff reserved area (12 bytes) 0x00 5400 adc1 contd adc _csr adc contro l/status register 0x00 0x00 5401 adc_cr1 adc configuration register 1 0x00 0x00 5402 adc_cr2 adc configuration register 2 0x00 0x00 5403 adc_cr3 adc configuration register 3 0x00 0x00 5404 adc_drh adc data register high 0xxx 0x00 5405 adc_drl adc data register low 0xxx
memory and register map stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 38 / 101 docid025118 re v 4 address block register lab el register name reset status 0x00 5406 adc_tdrh adc schmitt trigger disable register high 0x00 0x00 5407 adc_tdrl adc schmitt trigger disable register low 0x00 0x00 5408 adc_htrh adc high threshold r egister high 0x03 0x00 5409 adc_htrl adc high threshold register low 0xff 0x00 540a adc_ltrh adc low threshold register high 0x00 0x00 540b adc_ltrl adc low threshold register low 0x00 0x00 540c adc_awsrh adc analog watc hdog status register high 0x00 0x00 540d adc_awsrl adc analog watchdog status register low 0x00 0x00 540e adc _awcrh adc analog watchdog control register high 0x00 0x00 540f adc_awcrl adc analog watchdog control register low 0x 00 0x00 5410 to 0x00 57ff reserved area (1008 bytes) notes: (1) depends on the previous reset source. (2) write only register.
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 memory and regist er map docid025118 rev 4 39 / 101 6.2.3 cpu/swim/debug module/interrupt controller registers table 12: cpu/swim/debug module/interrupt controller registers address block register label register name reset status 0x00 7f00 cpu (1) a accumulator 0x00 0x00 7f01 pce program counter extended 0x00 0x00 7f02 pch program counter high 0x00 0x00 7f03 pcl program counter low 0x00 0x00 7f04 xh x index register high 0x00 0x00 7f05 xl x index register low 0 x00 0x00 7f06 yh y index register high 0x00 0x00 7f07 yl y index register low 0x00 0x00 7f08 sph stack pointer high 0x03 0x00 7f09 spl stack pointer low 0xff 0x00 7f0a ccr condition code register 0x28 0x 00 7f0b to 0x00 7f5f reserved area (85 bytes) 0x00 7f60 cpu cfg_gcr global configuration register 0x00 0x00 7f70 itc itc_spr1 interrupt software priority register 1 0xff 0x00 7f71 itc_spr2 interrupt software priority register 2 0xff 0x00 7f72 itc_spr3 interrupt software priority register 3 0xff 0x00 7f73 itc_spr4 interrupt software priority register 4 0xff 0x00 7f74 itc_spr5 interrupt software priority register 5 0xff 0x00 7f75 itc_spr6 interrupt software priority register 6 0xff 0x00 7f76 itc_spr7 interrupt software priority register 7 0xff 0x00 7f77 itc_spr8 interrupt software priority register 8 0xff 0x00 7f78 to 0x00 7f79 reserved area (2 bytes) 0x00 7f80 swim swim_csr swim control status register 0x00 0x00 7f81 to 0x00 7f8f reserved area (15 bytes) 0x00 7f90 dm dm_bk1re dm breakpoint 1 register extended byte 0xff 0x00 7f91 dm_bk1rh dm breakpoint 1 register high byte 0xff 0x00 7f92 dm_bk1rl dm breakpoint 1 register low byte 0xff
memory and register map stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 40 / 101 docid025118 re v 4 address block register label register name reset status 0x00 7f93 dm_bk2re dm breakpoint 2 register extended byte 0xff 0x00 7f94 dm_bk2rh dm breakpoint 2 register high byte 0xff 0x00 7f95 dm_bk2rl dm breakpoint 2 reg ister low byte 0xff 0x00 7f96 dm_cr1 dm debug module control register 1 0x00 0x00 7f97 dm_cr2 dm debug module control register 2 0x00 0x00 7f98 dm_csr1 dm debug module control/status register 1 0x10 0x00 7f99 dm_csr2 dm debug module control/status register 2 0x00 0x00 7f9a dm_enfctr dm enable function register 0xff 0x00 7f9b to 0x00 7f9f reserved area (5 bytes) notes: (1) accessible by debug module only
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 interrupt vector mapping docid025118 rev 4 41 / 101 7 interrupt vector mapping table 13: interrupt mapping irq no. source block description wakeup from halt mode wakeup from active - halt mode vector address reset reset yes yes 0x00 8000 trap software interrupt - - 0x00 8004 0 tli external top level interrupt - - 0x00 8008 1 awu auto wake up from halt - yes 0x00 800c 2 clk clock controller - - 0x00 8010 3 exti0 port a external interrup ts yes (1) yes (1) 0x00 8014 4 exti1 port b external interrupts yes yes 0x00 8018 5 exti2 port c external interrupts yes yes 0x00 801c 6 exti3 port d external interrupts yes yes 0x00 8020 7 exti4 port e external interrupts yes yes 0x00 8024 8 exti5 port f 0x00 8028 9 reserved - - 0x00 802c 10 spi end of transfer yes yes 0x00 8030 11 tim1 tim 1 update/ overflow/ underflow/ trigger/ break - - 0x00 8034 12 tim1 tim1 capture/ compare - - 0x00 8038 13 tim5 tim5 update/ overflow/ trigger - - 0x00 803c 14 tim5 tim5 capture/ compare - - 0x00 8040 15 r eserved - - 0x00 8044 16 reserved - - 0x00 8048 17 linuart tx complete - - 0x00 804c 18 linuart receive register data full - - 0x00 8050 19 i 2 c i 2 c interrupt yes yes 0x00 8054 20 reserved - - 0x00 8058 21 reserved - - 0x00 805c 22 adc1 adc1 end of conversion/ analog watchdog interrupt - - 0x00 8060 23 tim6 tim6 update/ overflow/ trigger - - 0x00 8064 24 flash eop/ wr_pg_dis - - 0x00 8068 no tes: (1) except pa1
option bytes stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 42 / 101 docid025118 re v 4 8 option bytes option bytes contain configurations for device hardware features as well as the memory protection of the device. they are stored in a dedicated block of the memory. except for the rop (read - out protection) byte, each option byte has to be stored twice, in a regular form (optx) and a complemented one (noptx) for redundancy. option bytes can be modified in icp mode (via swim) by accessing the eepro m address shown in the table below. option bytes can also be modified on the fly by the application in iap mode, except the rop option that can only be modified in icp mode (via swim). refer to the stm8s and stm8a flash programming manual (pm0051) and stm8 swim communication protocol and debug module user manual (um0470) for information on swim programming procedures. table 14: option bytes addr. option name option byte no. option bits factory default setting 7 6 5 4 3 2 1 0 0x4800 read - out protection (rop) opt0 rop [7:0] 0x00 0x4801 user boot code(ubc) opt1 ubc [7:0] 0x00 0x4802 nopt1 nubc [7:0] 0xff 0x4803 alternate function remapping (afr) opt2 afr7 afr6 afr5 afr4 afr3 afr2 afr1 afr0 0x00 0x4804 nopt2 nafr7 nafr6 nafr5 nafr4 nafr3 nafr2 nafr1 nafr0 0xff 0x4805 h miscell. option opt3 reserved hsi trim lsi_ en iwdg _hw wwdg _hw wwdg _halt 0x00 0x4806 nopt3 reserved nhsi trim nlsi_ en niwdg _hw nwwd g _hw nww g_hal t 0xff 0x4807 clock option opt4 reserved ext clk ckaw u sel prs c1 prs c0 0x00 0x4808 nopt4 reserved next clk ncka wuse l nprsc 1 npr sc0 0xff 0x4809 hse clock startup opt5 hsecnt [7:0] 0x00 0x480a nopt5 nhsecnt [7:0] 0xff
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 option bytes docid025118 rev 4 43 / 101 table 15: option byte description option byte no. description opt0 rop[7:0] memory readout protection (rop) 0xaa: enable readout protection (write access via swim protocol) n ote: refer to the family reference manual (rm0016) section on flash/eeprom memory readout protection for details. opt1 ubc[7:0] user boot code area 0x00: no ubc, no write - protection 0x01: page 0 defined as ubc, memory write - protected 0x02: pages 0 t o 1 defined as ubc, memory write - protected. page 0 and 1 contain the interrupt vectors. ... 0x7f: pages 0 to 126 defined as ubc, memory write - protected other values: pages 0 to 127 defined as ubc, memory write - protected note: refer to the family refer ence manual (rm0016) section on flash write protection for more details. opt2 afr[7:0] refer to following section for alternate function remapping decriptions of bits [7:2] and [1:0] respectively. opt3 hsitrim :high speed internal clock trimming re gister size 0: 3 - bit trimming supported in clk_hsitrimr register 1: 4 - bit trimming supported in clk_hsitrimr register lsi_en :low speed internal clock enable 0: lsi clock is not available as cpu clock source 1: lsi clock is available as cpu clock sou rce iwdg_hw : independent watchdog 0: iwdg independent watchdog activated by software 1: iwdg independent watchdog activated by hardware wwdg_hw : window watchdog activation 0: wwdg window watchdog activated by software 1: wwdg window watchdog acti vated by hardware wwdg_halt : window watchdog reset on halt 0: no reset generated on halt if wwdg active 1: reset generated on halt if wwdg active
option bytes stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 44 / 101 docid025118 re v 4 option byte no. description opt4 extclk : external clock selection 0: external crystal connected to oscin/oscout 1: external clo ck signal on oscin ckawusel :auto wake - up unit/clock 0: lsi clock source selected for awu 1: hse clock with prescaler selected as clock source for for awu prsc[1:0] awu clock prescaler 0x: 16 mhz to 128 khz prescaler 10: 8 mhz to 128 khz prescaler 11: 4 mhz to 128 khz prescaler opt5 hsecnt[7:0] :hse crystal oscillator stabilization time 0x00: 2048 hse cycles 0xb4: 128 hse cycles 0xd2: 8 hse cycles 0xe1: 0.5 hse cycles
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 option bytes docid025118 rev 4 45 / 101 8.1 stm8af6226/STM8AF6223/STM8AF6223a/stm8af6213 alternate function rema pping bits table 16: stm8af6226 alternate function remapping bits [7:2] for 32 - pin packages option byte no. description (1) opt2 afr7 alternate function remapping option 7 0: afr7 remapping option inactive: default alternate functions (2) 1: port c3 alternate function = tim1_ch1n; port c4 alternate function = tim1_ch2n. af r6 alternate function remapping option 6 0: afr6 remapping option inactive: default alternate function (2) . 1: port d7 alternate function = tim1_ch4. afr5 alternate function remapping option 5 0: afr5 remapping option inactive: default alternate function (2) . 1: port d0 alternate function = clk_cco. afr4 alternate function remapping option 4 0: afr4 remapping option inactive: default alternate functions (2) . 1: port b4 alternate function = adc_etr; port b5 alternate function = tim1_bkin. afr3 alternate function remapping option 3 0: afr3 remapping option inactive: default alternate function (2) . 1: port c3 alt ernate function = tli. afr2 alternate function remapping option 2 0: afr2 remapping option inactive: default alternate functions (2) . 1: port c4 alternate function = ain2; port d2 alternate function = ain3; port d4 alt ernate function = linuart_ck. notes: (1) do not use more than one remapping option in the same port. (2) refer to pinout description.
option bytes stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 46 / 101 docid025118 re v 4 table 17: stm8af6213/STM8AF6223 alternate function remapping bits [7:2] for 20 - pin packages option byte no. descr iption (1) opt2 afr7 alternate function remapping option 7 0: afr7 remapping option inactive: default alternate functions (2) 1: port c3 alternate function = tim1_ch1n; port c4 alter nate function = tim1_ch2n. afr6 alternate function remapping option 6 reserved. afr5 alternate function remapping option 5 reserved. afr4 alternate function remapping option 4 0: afr4 remapping option inactive: default alternate functions. (2) 1: port b4 alternate function = adc_etr; port b5 alternate function = tim1_bkin. afr3 alternate function remapping option 3 0: afr3 remapping option inactive: default alternate function (2) . 1: port c3 alternate function = tli. afr2 alternate function remapping option 2 0: afr2 remapping option inactive: default alternate functions (2) . 1: port d4 alternate function = linuart_ck. notes: (1) do not use more than one remapping option in the same port. (2) refer to pinout description.
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 option bytes docid025118 rev 4 47 / 101 table 18: STM8AF6223a alternate function remapping bits [7:2] for 20 - pin packages option byte no. description (1) opt2 afr7 alte rnate function remapping option 7 0: afr7 remapping option inactive: default alternate functions (2) 1: port c4 alternate function = tim1_ch2n. afr6 alternate function remapping option 6 reserved. afr5 alternate funct ion remapping option 5 reserved. afr4 alternate function remapping option 4 0: afr4 remapping option inactive: default alternate functions (2) . 1: port b4 alternate function = adc_etr; port b5 alternate function = tim 1_bkin. afr3 alternate function remapping option 3 reserved. afr2 alternate function remapping option 2 0: afr2 remapping option inactive: default alternate functions (2) . 1: port d4 alternate function = linuart_ck. notes: (1) do not use more than one remapping option in the same port. (2) refer to pinout description. table 19: stm8af6226 alternate function remapping bits [1:0] for 32 - pin packages afr1 option bit value afr0 option bit value i/o port alternate function mapping 0 0 afr1 and afr0 remapping options inactive: default alternate functions (1) 0 1 pc5 tim5_ch1 pc6 tim1_ch1 pc7 tim1_ch2 1 0 pa3 spi_nss pd2 tim5_ch3 1 (2) 1 (2) pd2 tim5_ch3 pc5 tim5_ch1 pc6 tim1_ch1 pc7 tim1_ch2
option bytes stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 48 / 101 docid025118 re v 4 afr1 option bit value afr0 option bit value i/o port alternate function mapping pc2 tim1_ch3n pc1 tim1_ch2n pe5 tim1_ch1n pa3 linuart_tx pf4 linuar t_rx notes: (1) refer to pinout description. (2) if both afr1 and afr0 option bits are set, the spi hardware nss management feature is no more available. if this remapping option is selected and the spi is enabled, the ssm bit must be configured in the s pi_cr2 register to select software nss management. table 20: stm8af6213/STM8AF6223 alternate function remapping bits [1:0] for 20 - pin packages afr1 option bit value afr0 option bit value i/o port alternate function mapping 0 0 afr1 and afr0 re mapping options inactive: default alternate functions (1) 0 1 pc5 tim5_ch1 pc6 tim1_ch1 pc7 tim1_ch2 1 0 pa3 spi_nss pd2 tim5_ch3 1 1 pd2 tim5_ch3 pc5 tim5_ch1 pc 6 tim1_ch1 pc7 tim1_ch2 pc2 not available pc1 not available pe5 not available pa3 spi_nss pf4 not available notes: (1) refer to pinout description.
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 option bytes docid025118 rev 4 49 / 101 table 21: STM8AF6223a alternate function remapping bits [1 :0] for 20 - pin packages afr1 option bit value afr0 option bit value i/o port alternate function mapping 0 0 afr1 and afr0 remapping options inactive: default alternate functions (1) 0 1 pc5 tim5_ch1 pc6 tim1_ch1 pc7 tim1_ch2 1 0 pa3 not available pd2 tim5_ch3 1 (2) 1 (2) pd2 tim5_ch3 pc5 tim5_ch1 pc6 tim1_ch1 pc7 tim1_ch2 pc2 not available pc1 not available pe5 not available pa3 not available pf4 not available notes: (1) refer to pinout description. (2) if both afr1 and afr0 option bits are set, the spi hardware nss management feature is no more avai lable. if this remapping option is selected and the spi is enabled, the ssm bit must be configured in the spi_cr2 register to select software nss management.
electrical characteristics stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 50 / 101 docid025118 re v 4 9 electrical characteristics 9.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 9.1.1 minimum and maximum values unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at t a = - 40 c, t a = 25 c and t a = t amax (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not t ested in production. 9.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 5.0 v. they are given only as design guidelines and are not tested . typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range. 9.1.3 typical curves unless o therwise specified, all typical curves are given only as design guidelines and are not tested. 9.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in the following figure. figure 7 : pin loading conditions 5 0 p f stm 8 p i n
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 electrical characteristics docid025118 rev 4 51 / 101 9.1.5 pin input voltage the input voltage measurement on a pin of the device is described in the following figure. figure 8 : pin input voltage 9.2 absolute maximum ratings stresses above those listed as absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 22: voltage characteristics symbol ratings min max unit v ddx - v ss supply voltage (1) - 0.3 6.5 v v in input voltage on true open drain pins (2) v ss - 0.3 6.5 input voltag e on any other pin (2) v ss - 0.3 v dd + 0.3 |v ddx - v dd | variations between different power pins - 50 mv |v ssx - v ss | variations between all the different ground pins - 50 v esd electrostatic dischar ge voltage see "absolute maximum ratings (electrical sensitivity)" notes: (1) all power (vdd) and ground (vss) pins must always be connected to the external power supply (2) iinj(pin) must never be exceeded. this is implicitly insured if vin maximum i s respected. if vin maximum cannot be respected, the injection current must be limited externally to the iinj(pin) value. a positive injection is induced by vin>vdd while a n egative injection is induced by vin electrical characteristics stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 52 / 101 docid025118 re v 4 symbol ratings max (1) unit i io output current sunk by any i/o and control pin 20 output current source by any i/os and control pin - 20 i inj(pin) (3) (4) injected current on nrst pin 4 injected current on oscin pin 4 injected current on any other pin (5) 4 i inj(p in) (3) total injected current (sum of all i/o and control pins) (5) 20 notes: (1) data based on characterization results, not tested in production. (2) all power (vdd) and ground (vss) pins must always be connected to the external supply. (3) iinj(pin) must never be exceeded. this is implicitly insured if vin maximum is respected. if vin maximum cannot be respected, the injection current must be limited externally to the iinj(pin) value. a positive injection is induced by vin>vdd while a negative injection is induced by vin st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 electrical cha racteristics docid025118 rev 4 53 / 101 9.3 operating conditions table 26: general operating conditions symbol parameter conditions min max u nit f cpu internal cpu clock frequency 0 16 mhz v dd standard operating voltage 3.0 5.5 v vcap (1) c ext : capacitance of external capacitor 470 3300 nf esr of external capacitor at 1 mh z (2) - 0.3 esl of external capacitor - 15 nh p d (3) power dissipation at t a = 85 c for suffix a tssop20 - 182 mw lqfp32 - 333 power dissipation at t a = 125 c for suffix c tssop20 - 45 lqfp32 - 83 power dissipation at t a = 150 c for suffix d tssop20 - tbd (4) lqfp32 - tbd (4) t a ambient temperature for a suffix version maximum power dissipation - 40 85 c ambient temperature for c suffix version maximum power dissipation - 40 125 ambient temperature for d suffix version maximum power dissipation - 40 150 t j junction te mperature range a suffix version - 40 90 c suffix version - 40 130 d suffix version - 40 155 notes: (1) care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter dependency on temperature, d c bias and frequency in addition to other factors. the parameter maximum value must be respected for the full application range. (2) this frequency of 1 mhz as a condition for vcap parameters is given by design of internal regulator (3) to calculate p dmax ( t a ), use the formula p dmax = (t jmax - t a )/ ja (see section 6: "product overview" ). (4) tbd stands for "to be defined".
electrical characteristics stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 54 / 101 docid025118 re v 4 figure 9 : fcpumax versus vdd table 27: operating conditions at power - up/po wer - down symbol parameter conditions min typ max unit t vdd v dd rise time rate 2 (1) - s/v v dd fall time rate (2) 2 (1) - t temp reset release delay v dd rising - 1.7 ms v it+ power - on reset threshold 2.6 (1) 2.7 2.85 v v it - brown - out reset threshold 2.5 2.65 2.8 (1) v hys(bor) brown - out reset hysteresis 70 (1) - mv notes: (1) guaranteed by design, not tested in production (2) reset is always generated after a t temp delay. the application must ensure that v dd is still abov e the minimum operating voltage (v dd min) when the t temp delay has elapsed.
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 electrical characteristics docid025118 rev 4 55 / 101 9.3.1 vcap external capacitor stabilization for the main regulator is achieved connecting a n external capacitor c ext to the v cap pin. c ext is specified in the operating conditions section. care should be taken to limit the series inductance to less than 15 nh. figure 10 : external capacitor cext 1. esr is the equivalent s eries resistance and esl is the equivalent inductance. 9.3.2 supply current characteristics the current consumption is measured as described in section 6.3: "interrupt controller" . 9.3.2.1 total current consumption in run mode the mcu is placed under the following conditions: ? all i/o pin s in input mode with a static value at v dd or v ss (no load) ? all peripherals are disabled (clock stopped by peripheral clock gating registers) except if explicitly mentioned. subject to general operating conditions for v dd and t a . unless otherwise specif ied, data are based on characterization results, and not tested in production. table 28: total current consumption with code execution in run mode at vdd = 5 v symbol parameter conditions typ max unit i dd(run) supply current in run mode, code executed from ram f cpu = f master = 16mhz hse crystal osc. (16 mhz) 2.3 - ma hse user ext. clock (16 mhz) 2 2.35 hsi rc osc. (16 mhz) 1.7 2 (1) f cpu = f master /128= 125 khz hse user ext. clock (16 mhz) 0.86 - hsi rc osc. (16 mhz) 0.7 0.87 f cpu = f master /128= 15.625khz hsi rc osc. (16 mhz/8) 0.46 0.58 f cpu = f master = 28khz lsi rc osc. (128 khz) 0.41 0.55 supply current in run mode, code executed from flash f cpu = f master = 16mhz hse crystal osc. (16 mhz) 4.5 - hse user ext. clock (16 mhz) 4.3 4.75 c rlea k es r e s l
electrical characteristics stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 56 / 101 docid025118 re v 4 symbol parameter conditions typ max unit hsi rc osc. (16 mhz) 3.7 4.5 (1) i dd(run) supply current in run mode, code executed fr om flash f cpu = f master = 2mhz hsi rc osc. (16 mhz/8) (2) 0.84 2 (1) ma f cpu = f master /128 = 125khz hsi rc osc. (16 mhz) 0.72 0.9 f cpu = f master /128 = 15.625 khz hsi rc osc. (16 mhz/8) 0.46 0.58 f cpu = f master = 128 khz lsi rc osc. (128 khz) 0.42 0.57 notes: (1) tested in production. (2) default clock configuration measured with all peripherals off. table 29: total current consumption with c ode execution in run mode at vdd = 3.3 v symbol parameter conditions typ max (1) unit i dd(run) supply current in run mode, code executed from ram f cpu = f master =16mhz hse crystal osc. (16 mhz) 1.8 - ma hse user ext. clock (16 mhz) 2 2.3 hsi rc osc. (16 mhz) 1.5 2 f cpu = f master /128 = 125khz hse user ext. clock (16 mhz) 0.81 - hsi rc osc. (16 mhz) 0.7 0.87 f cpu = f master / 128 = 15.625khz hsi rc osc. (1 6 mhz/8) 0.46 0.58 f cpu = f master =128khz lsi rc osc. (128 khz) 0.41 0.55 supply current in run mode, code executed from flash f cpu = f master = 16mhz hse crystal osc. (16 mhz) 4 - hse user ext. clock (16 mhz) 3.9 4.7 hsi rc osc. (16 mhz) 3.7 4.5 f cpu = f master =2mhz hsi rc osc. (16 mhz/8) (2) 0.84 1.05 f cpu = f master / 128 = 125khz hsi rc osc. (16 mhz) 0.72 0.9 f cpu = f master /128 = 15.625khz hsi rc osc. (16 mhz/8) 0.46 0.58
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 electrical characteristics docid025118 rev 4 57 / 101 symbol parameter conditions typ max (1) unit f cpu = f master =128khz lsi rc osc. (128 khz) 0.42 0.57 notes: (1) data based on characterization results, not tested in production. (2) default clock configuration measured with all peripherals off. 9.3.2.2 total current consumption in wait mode unless otherwise specified, data based are on characterization results, and not tested in production. table 30: tota l current consumption in wait mode at vdd = 5 v symbol parameter conditions typ max unit i dd(wfi) supply current in wait mode f cpu = f master = 16mhz hse crystal osc. (16 mhz) 1.6 - ma hse user ext. clock (16 mhz) 1.1 1.3 hsi rc osc . . (16 mhz) 0.89 1.5 (1) f cpu = f master /128 = 125khz hsi rc osc. (16 mhz) 0.7 0.88 f cpu = f master /128 = 15.625khz hsi rc osc. (16 mhz/8) (2) 0.45 0 .57 f cpu = f master = 128khz lsi rc osc. (128 khz) 0.4 0.54 notes: (1) tested in production (2) default clock configuration measured with all peripherals off.
electrical characteristics stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 58 / 101 docid025118 re v 4 table 31: total current consumption in wait mode at vdd = 3.3 v symbol para meter conditions typ max (1) unit i dd(wfi) supply current in wait mode f cpu = f master = 16mhz hse crystal osc. (16 mhz) 1.1 - ma hse user ext. clock (16 mhz) 1.1 1.3 hsi rc osc. (16 mhz) 0.89 1.1 f cpu = f master / 128 = 125khz hsi rc osc. (16 mhz) 0.7 0.88 f cpu = f master / 128 = 15.625khz hsi rc osc. (16 mhz/8) (2) 0.45 0.57 f cpu = f master = 128khz lsi rc osc. (128 khz) 0.4 0.54 notes: (1) data based on characterization results, not tested in production. (2) default clock configuration measured with all peripherals off. 9.3.2.3 total current consumption in active halt mode unless otherwise specified, data are based on characterization results and not tested in production. table 32: total current consumption in active halt mode at vdd = 5 v symbol parameter conditi ons typ max at 85 c max at 125 c max at 150 c unit main voltage regulator (mvr) (1) flash mode (2) clock source i dd(ah) supply current in active halt mode on operating mode hse crystal osc. (16 mhz) 1030 - - - a i dd(ah) supply current in active halt mode on operating mode lsi rc osc. (128 khz) 200 260 300 - i dd(ah) supply current in active halt mode on power - down mode hse crystal osc. (16 mhz) 970 - - - i dd(ah) supply current in active halt mode on power - down mode lsi rc osc. (128 khz) 150 200 230 -
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 electrical characteristics docid025118 rev 4 59 / 101 symbol parameter conditi ons typ max at 85 c max at 125 c max at 150 c unit main voltage regulator (mvr) (1) flash mode (2) clock source i dd(ah) supply current in active halt mode off operating mode lsi rc osc. (128 khz) 66 85 140 200 i dd(ah) supply current in active halt mode power - down mode lsi rc osc. (128 khz) 10 20 40 - notes: (1) configured by the regah bit in the clk_ickr register. (2) configured by the ahalt bit in the flash_cr1 register. table 33: total cur rent consumption in active halt mode at vdd = 3.3 v symbol parameter conditions typ max at 85 c (1) max at 125 c (1) unit main voltage regulator (mvr) (2) flash mode (3) clock source i dd(ah) supply current in active halt mode on operating mode hse crystal osc. (16 mhz) 550 - - a i dd(ah) supply current in active halt mode on operating mode lsi rc osc. (128 khz) 200 260 290 i dd(ah) power - down mode hse crystal osc. (6 mhz) 970 - - i dd(ah) supply current in active halt mode lsi rc osc. (128 khz) 1 50 200 230 i dd(ah) off operating mode lsi rc osc. (128 khz) 66 80 105 i dd(ah) power - down mode 10 18 35 notes: (1) data based on characterization results, not tested in production (2) configured by the regah bit in the cl k_ickr register. (3) configured by the ahalt bit in the flash_cr1 register.
electrical characteris tics stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 60 / 101 docid025118 re v 4 9.3.2.4 total current consumption in halt mode unless otherwise specified, da ta based are on characterization results, and not tested in production table 34: total current consumption in halt mode at vdd = 5 v symbol parameter conditions typ max at 85 c max at 125 c max at 150 c unit i dd(h) supply current in halt m ode flash in operating mode, hsi clock after wakeup 63 75 105 - a flash in power - down mode, hsi clock after wakeup 6.0 20 (1) 55 (1) 80 (1) notes: (1) tested in production. table 35: total current consumption in halt mode at vdd = 3.3 v symbol parameter conditions typ max at 85 c (1) max at 125 c (1) unit i dd(h) supply current in halt mode flash in operating mode, h si clock after wakeup 60 75 100 a flash in power - down mode, hsi clock after wakeup 4.5 17 30 notes: (1) data based on characterization results, not tested in production
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 electrical characteristics docid025118 rev 4 61 / 101 9.3.2.5 low power mode wakeup times table 36: wakeup times symbol parameter conditions typ max (1) unit t wu(wfi) wakeup time from wait mode to run mode (2) 0 to 16 mhz - see note (3) s f cpu = f master = 16 mhz 0.56 - t wu(ah) wakeup time active halt mode to run mode (2) mvr voltage regulator on (4) flash in operating mode (5) hsi (after wakeup) 1 (6) 2 (6) wakeup time active halt mode to run mode (2) mvr voltage regulator on (4) flas h in power - down mode (5) hsi (after wakeup) 3 (6) - wakeup time active halt mode to run mode (2) mvr voltage regulator off (4) flash in operating mode (5) hsi (after wakeup) 48 (6) - wakeup time active halt mode to run mode (2) mvr voltage regulator off (4) flash in power - down mode (5) hsi (after wakeup) 50 (6) - t wu(h) wakeup time from halt mode to run mode (2) flash in operating mode (5) 52 - flash in power - down mode (5) 54 ? notes: (1) data guaranteed by design, not tested in production. (2) measured from interrupt event to interrup t vector fetch. (3) twu(wfi) = 2 x 1/fmaster + 67 x 1/fcpu. (4) configured by the regah bit in the clk_ickr register. (5) configured by the ahalt bit in the flash_cr1 register. (6) plus 1 lsi clock depending on synchronization.
electrical characteristics stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 62 / 101 docid025118 re v 4 9.3.2.6 total current consumpti on and timing in forced reset state table 37: total current consumption and timing in forced reset state symbol parameter conditio ns typ max (1) unit i dd(r) supply current in reset state (2) v dd = 5 v 400 - a v dd = 3.3 v 300 - t resetbl reset pin release to vector fetch - 150 s notes: (1) data guaranteed by design, not tested in production. (2) characterized with all i/os tied to v ss . 9.3.2.7 current consumption of on - chip peripherals subject to general operating conditions for v dd and t a . hsi internal rc/f cpu = f master = 16 mhz, v dd = 5 v table 38: peripheral current consumption sy mbol parameter typ. unit i dd(tim1) tim1 supply current (1) 210 a i dd(tim5) tim5 supply current (1) 130 i dd(tim6) tim6 timer supply current (1) 50 i dd(uart1) linuart supply current (2) 120 i dd(spi) spi supply current (2) 45 i dd(i 2 c) i 2 c supply current (2) 65 i dd(adc1) adc1 supply current when converting (3) 1000 notes: (1) data based on a differential i dd measurement between reset configuration and timer counter running at 16 mhz. no ic/oc programmed (no i/o pads tog gling). not tested in production. (2) data based on a differential i dd measurement between the on - chip peripheral when kept under reset and not clocked and the on - chip peripheral when clocked and not kept under reset. no i/o pads toggling. not tested in pr oduction. (3) data based on a differential i dd measurement between reset configuration and continuous a/d conversions. not tested in production.
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 electrical characteristics docid025118 rev 4 63 / 101 9.3.2.8 current consumption curves the following figures show typical current consumption measured with code executing in ram. figure 11 : typ idd(run) vs. vdd hse user external clock, fcpu = 16 mhz figure 12 : typ idd(run) vs . fcpu hse user external clock, vdd = 5 v
electrical characteristics stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 64 / 101 docid025118 re v 4 figure 13 : typ idd(run) vs. vdd hsi rc osc, fcpu = 16 mhz figure 14 : typ idd(wfi) vs. vdd hse user external clock, fcpu = 16 mhz figure 15 : typ idd(wfi) vs. fcpu hse user external clock, vdd = 5 v
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 electrical characteristics docid025118 rev 4 65 / 101 figure 16 : typ idd(wfi) vs. vdd hsi rc osc, fcpu = 16 mhz 9.3.3 external clock sources and timing characteristics hse user external clock subject to general operating conditions for v dd and t a . table 39: hse user external clock characteristics symbol parameter conditions min max unit f hse_ext use r external clock source frequency 0 16 mhz v hseh (1) oscin input pin high level voltage 0.7 x v dd v dd + 0.3 v v v hsel (1) oscin input pin low level voltage v ss 0 .3 x v dd i leak_hse oscin input leakage current v ss < v in < v dd - 1 +1 a notes: (1) data based on characterization results, not tested in production.
electrical characteristics stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 66 / 101 docid025118 re v 4 figure 17 : hse external clock source hse crystal/ceramic resonator oscillator the hse clock can be supplied with a 1 to 16 mhz crystal/ceramic resonator oscillator. all the information given in this paragraph is based on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possible to the oscil lator pins in order to minimize output distortion and start - up stabilization time. refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...). table 40: hse oscillator characteristics symbol parameter conditions min typ max unit f hse external high speed oscillator frequency 1 - 16 mhz r f feedback resistor - 220 - k? c (1) recommended load capacitance (2) - - 20 pf i dd(hse) hse oscillator power consumption c = 20 pf, f osc = 16 mhz - - 6 (startup) 1.6 (stabilized) (3) ma c = 10 pf, f osc =16 mhz - - 6 (startup) 1.2 (stabilized) (3) g m oscillator transconductance 5 - - ma/v t su(hse) (4) startup time v dd is stabilized - 1 - ms notes: (1) c is approximately equivalent to 2 x crystal cload. (2) the oscillator selection can be optimized in terms of supply current using a high quality resonator with small rm value. refer to crystal manufacturer for more details
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 electrical characteristics docid025118 rev 4 67 / 101 (3) data based on characterization results, not tested in production. (4) tsu(hse) is the start - up time measured fro m the moment it is enabled (by software) to a stabilized 16 mhz oscillation is reached. this value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. figure 18 : hse oscillat or circuit diagram hse oscillator critical g m equation g mcrit = (2 f hse ) 2 r m (2co + c) 2 r m : notional resistance (see crystal specification) l m : notional inductance (see crystal specification) c m : notional capacitance (see crystal specification) co: shunt capacitance (see crystal specification) c l1 = c l2 = c: grounded external capacitance g m >> g mcrit
electrical characteristics stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 68 / 101 docid025118 re v 4 9.3.4 internal clock sources and timing characteristics subject to general operating conditions for v dd and t a . high speed internal rc oscillator (hsi) table 41: hsi oscillator characteristics symbol parameter conditions min typ max unit f hsi frequency - 16 - mhz acc hsi h si oscillator user trimming accuracy trimmed by the application for any v dd and t a conditions (1) - 1.0 (2) - 1.0 (2) % - 0.5 (2) - 0.5 (2) hsi oscillator accuracy (factory calibrated) 3.0v v dd 5.5v, - 40ct a 150 c - 5.0 - 5.0 t su(hsi) hsi oscillator wakeup time - - 2.0 (3) s i dd(hsi) hsi oscillator power consumption - 170 250 (4) a notes : (1) refer to application note. (2) depending on option byte setting (opt3 and nopt3) (3) guaranteed by design, not tested in production (4) data based on characterization results, not tested in production. low speed internal rc oscillator (lsi) subject to general operating conditions for v dd and t a . unless otherwise specified, data are based on characterization results, and not tested in production. table 42: lsi oscillator characteristics symbol parameter min typ max unit f lsi frequenc y 110 (1) 128 150 (1) khz t su(lsi) lsi oscillator wake - up time - - 7 s i dd(lsi) lsi oscillator power consumption - 5 - a notes: (1) tested in production.
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 electrical characteristics docid025118 rev 4 69 / 101 9.3.5 memory characteristics ram and hardware registers table 43: ram and hardware registers symbol parameter conditions min unit v rm data retention mode (1) halt mode (or reset) v it - max (2) v notes: (1) minimum supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware registers (only in halt mode). guara nteed by design, not tested in production. (2) refer to the operating conditions section for the value of vit - max flash program memory/data eeprom memory general conditions: t a = -- 40 to 150 c. table 44: flash program memory/data eeprom memory symbol parameter conditions min typ max unit v dd operating voltage (all modes, execution/ write/erase f cpu 16 mhz with 0 ws 3.0 - 5.5 v operating voltage (code execution) 2.6 - 5.5 t prog standard programming time (including erase) for byte/word/block (1 byte/4 bytes/64 bytes) - 6.0 6.6 ms fast programming time for 1 block (64 by tes) - 3.0 3.33 t erase erase time for 1 block (64 bytes) - 3.0 3.33 table 45: flash program memory symbol parameter conditions min max unit t we temperature for writing and erasing - 40 150 c n we flash program memory endur ance (erase/write cycles) (1) t a = +25 c 1000 - cycles t ret data retention time t a = 25c 40 - years t a = 55c 20 - notes: (1) the physical granularity of the memory is 4 bytes, so cycling is p erformed on 4 bytes even when a write/erase operation addresses a single byte.
electrical characteristics stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 70 / 101 docid025118 re v 4 table 46: data memory symbol parameter conditions min max unit t we temperature for writing and erasing - 40 150 c n we data memory endurance (erase/write cycl es) (1) t a = +25 c 300k - cycles t a = -- 40 to 125 c 100k (2) - t ret data retention time t a = 25c 40 (3) - years t a = 55c 20 (2) (3) - notes: (1) the physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte. (2) more inf ormation on the relationship between data retention time and nmber of write/erase cycles is available in a separate technical document. (3) retention time for 256b of data memory after up to 1000 cycles at 125 c. 9.3.6 i/o port pin characteristics general characteristics subject to general operating conditions for v dd and t a unless otherwise specified. all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull - up or pull - down resistor. table 47: i/o static characteristics symbol parameter conditions min typ max unit v il input low level voltage v dd = 5 v - 0.3 v - 0.3 x v dd v v ih input hi gh level voltage 0.7 x v dd - v dd + 0.3 v hys hysteresis (1) - 700 - mv r pu pull - up resistor v dd = 5 v, v in = v ss 30 55 80 k t r , t f rise and fall time (10 % - 90 %) fast i/os. load = 50 pf - - 35 (2) ns standard and high sink i/os. load = 50 pf - - 125 (2) fast i/os. load = 20 pf - - 20 (2) standard and high s ink i/os. load = 20 pf - - 50 (2) i lkg digital input leakage current v ss v in v dd - - 1 (3) a i lkg ana analog input leakage current v ss v in v dd - 40 c t a 125 c - - 250 (3) na
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 electrical characteristics docid025118 rev 4 71 / 101 symbol parameter conditions min typ max unit v ss v in v dd - 40 c a - - 500 (3) i lkg(inj) leakage current in adjacent i/o injection current 4 ma - - 1 (3) a notes: (1) hysteresis voltage between schmitt trigger switching levels. based on ch aracterization results, not tested in production. (2) data based on characterisation results, not tested in production. (3) data guaranteed by design. figure 19 : typical vil and vih vs vdd @ 4 temperatures figure 20 : typical pull - up resistance vs vdd @ 4 temperatures
electrical characteristics stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 72 / 101 docid025118 re v 4 figure 21 : typical pull - up current vs vdd @ 4 temperatures table 48: output driving current (standard ports) symbol parameter conditions min max unit v ol output low level with 8 pins sunk i io = 10 ma, v dd = 5 v - 2.0 v output low level with 4 pins sunk i io = 4 ma,v dd = 3.3 v - 1.0 (1) v oh output high level with 8 pins sourced i io = 10 ma, v dd = 5 v 2.8 - output high level with 4 pins sourced i io = 4 ma, v dd = 3.3 v 2.1 (1) - notes: (1) data based on characterization results, not tested in production table 49: output driving current (true open drain ports) symbol parameter conditions max unit v ol output low level with 2 pins sunk i io = 10 ma, v dd = 5 v 1 .0 v v ol output low level with 2 pins sunk i io = 10 ma, v dd = 3.3 v 1.5 (1) v ol output low level with 2 pins sunk i io = 20 ma, v dd = 5 v 2.0 (1) notes: (1) data based on characterization results, not tested in production table 50: output driving current (high sink ports) symbol parameter conditions min max unit v ol output low level with 8 pins sunk i io = 10 ma, v dd = 5 v - 0.8 v v ol output low level with 4 pins sunk i io = 10 ma, v dd = 3.3 v - 1.0 (1) v output low level with 4 p ins sunk i io = 20 ma, v dd = 5 v - 1.5 (1)
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 electrical characteristics docid025118 rev 4 73 / 101 symbol parameter conditions min max unit v oh output high level with 8 pins sourced i io = 10 ma, v dd = 5 v 4.0 - output high level with 4 pins sourced i io = 10 ma, v dd = 3.3 v 2.1 (1) - output high level with 4 pins sourced i io = 20 ma, v dd = 5 v 3.3 (1) - notes: (1) data based on characterization results, not tested in production figure 22 : typ . vol @ vdd = 5 v (standard ports) figure 23 : typ. vol @ vdd = 3.3 v (standard ports)
electrical characteristics stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 74 / 101 docid025118 re v 4 figure 24 : typ. vol @ vdd = 5 v (true open drain ports) figure 25 : typ. vol @ vdd = 3.3 v (true open drain ports)
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 electrical characteristics docid025118 rev 4 75 / 101 figure 26 : typ. vol @ vdd = 5 v (high sink ports) figure 27 : typ. vol @ vdd = 3.3 v (high sink ports)
electrical characteristics stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 76 / 101 docid025118 re v 4 figure 28 : typ. vdd - voh@ vdd = 5 v (standard p orts) figure 29 : typ. vdd - voh @ vdd = 3.3 v (standard ports)
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 electrical characteristics docid025118 rev 4 77 / 101 figure 30 : typ. vdd - voh@ vdd = 5 v (high sink ports) figure 31 : typ. vdd - voh@ vdd = 3.3 v (high sink ports) 9.3.7 reset pin characteristics subject to general operating conditions for v dd and t a unless otherwise specified. table 51: nrst pin characteristics symbol paramet er conditions min typ max unit v il(nrst) nrst input low level voltage (1) - 0.3 - 0.3 x v dd v v ih(nrst) nrst input high level voltage (1) i ol =2 ma 0.7 x v dd - v dd + 0.3 v ol(nrst) nrst output low level voltage (1) - - 0.5 r pu(nrst) nrst pull - up resistor (2) 30 55 80 k
electrical characteristics stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 78 / 101 docid025118 re v 4 symbol paramet er conditions min typ max unit t ifp(nrst) nrst input filtered pulse (3) - - 75 ns t infp(nrst) nrst input not filtered pulse (3) 500 - - t op(nrst) nrst output pulse (3) 20 - - s notes: (1) data based on charac terization results, not tested in production. (2) the r pu pull - up equivalent resistor is based on a resistive transistor (3) data guaranteed by design, not tested in production. figure 32 : typical nrst vil and vih vs vdd @ 4 temp eratures figure 33 : typical nrst pull - up resistance vs vdd @ 4 temperatures
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 electrical characteristics docid025118 rev 4 79 / 101 figure 34 : typical nrst pull - up current vs vdd @ 4 temperatures the reset network shown in the following figure protects the device against parasitic resets. the user must ensure that the level on the nrst pin can go below v il(nrst) max. (see section 11.3.6: "i/o port pin characteristics" ), otherwise the reset is not taken into account interna lly. for power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. if nrst signal is used to reset external circuitry, attention must be taken to the charge/discharge time of the ext ernal capacitor to fulfill the external devices reset timing conditions. minimum recommended capacity is 100 nf. figure 35 : recommended reset pin protection external reset circuit (optional) 0.1 f nrst vdd rpu filter internal reset stm8
electrical characteristics stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 80 / 101 docid025118 re v 4 9.3.8 spi serial peripheral interface unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature, f master frequency and v dd supply voltage conditions. t master = 1/f master . refer to i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso). table 52: spi characteristics symbol parameter conditions (1) min max unit f sck 1/t c(sck) spi clock frequency master mode 0 8 mhz f sck 1/t c(sck) spi clock frequency slave mode 0 6 mhz t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 30 pf 25 ns t su(nss) (2) nss setup time slave mode 4 x t master t h(nss) (2) nss hold time slave mode 70 t w(sckh) (2) t w(sc kl) (2) sck high a nd low time master mode t sck /2 - 15 t sck /2 +15 t su(mi) (2) t su(si) (2) data input setup time master mode 5 slave mode 5 t h(mi) (2) t h(si) (2) data input hold time master mode 7 slave mode 10 t a(so) (2) (3) data output access time slave mode 3 x t ma ster t dis(so) (2) (4) data output disable time slave mode 25 t v(so) (2) data output valid time slave mode (after enable edge) 65 t v(mo) (2) data output valid time master mode(after enable edge) 36 t h(so) (2) data output hold time slave mode(after enable edge) 27 t h(mo) (2) data output hold time master mode (after enable edge) 11 notes: (1) parameters are given by selecting 10 mhz i/o output frequency. (2) values based on design simulation and/or characterization results, and not tested in production . (3) min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. (4) min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi - z.
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 electrical characteristics docid025118 rev 4 81 / 101 fi gure 36 : spi timing diagram - slave mode and cpha = 0 figure 37 : spi timing diagram - slave mode and cpha = 1 1. measurement points are made at cmos levels: 0.3 vdd and 0.7 vdd.
electrical characteristics stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 82 / 101 docid025118 re v 4 figure 38 : spi timing diagram - master mode(1) 1. measurement points are made at cmos levels: 0.3 vdd and 0.7 vdd.
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 electrical characteristics docid025118 rev 4 83 / 101 9.3.9 i2c interface characteristics table 53: i2c characteristics symbol parameter standard mode i 2 c fast mode i 2 c (1) unit min (2) max (2) min (2) max (2) t w(scll) scl clock low time 4.7 - 1.3 - s t w(sclh) scl clock high time 4.0 - 0.6 - t su(sda) sda setup time 250 - 100 - ns t h(sda) sda data hold time - (3) 3450 - (4) 900 (3) t r(sda) t r(scl) sda and scl rise time - 1000 - 300 t f(sda) t f(scl) sda and scl fall time - 300 - 300 t h(sta) start condition ho ld time 4.0 - 0.6 - s t su(sta) repeated start condition setup time 4.7 - 0.6 - t su(sto) stop condition setup time 4.0 - 0.6 - t w(sto:sta) stop to start condition time (bus free) 4.7 - 1.3 - s t sp pulse width of spikes suppressed by the inp ut filter 0 50 (5) 0 50 (5) ns c b capacitive load for each bus line - 400 - 400 pf notes: (1) fmaster, must be at least 8 mhz to achieve max fast i2c speed (400khz) ( 2) data based on standard i2c protocol requirement, not tested in production (3) the maximum hold time of the start condition has only to be met if the interface does not stretch the low time (4) the device must internally provide a hold time of at least 30 0 ns for the sda signal in order to bridge the undefined region of the falling edge of scl (5) the minimum width of the spikes filtered by the analog filter is above tsp(max).
electrical characteristics stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 84 / 101 docid025118 re v 4 figure 39 : typical application with i2c bus and timi ng diagram 1. measurement points are made at cmos levels: 0.3 x vdd and 0.7 x vdd. 9.3.10 10 - bit adc characteristics subject to general operating conditions for v dd , f mas ter , and t a unless otherwise specified. table 54: adc characteristics symbol parameter conditions min typ max unit f adc adc clock frequency v dd =3 to 5.5 v 1 - 4 mhz v dd =4.5 to 5.5 v 1 - 6 v ain conversion voltage range (1) v ss - v dd v v bgref internal bandgap reference voltage v dd =3 to 5.5 v 1.19 (2) 1.22 1.25 (2) v c adc internal sample a nd hold capacitor - 3 - pf t s (1) minimum sampling time f adc = 4 mhz - 0.75 - s f adc = 6 mhz - 0.5 - t stab wake - up time from standby - 7 - s t conv minimum total conversion time (including sampling time, 10 - bit resolution) f adc = 4 mhz 3.5 s f adc = 6 mhz 2.33 s 14 1/f adc notes: (1) during the sample time the input capacitance c ain (3 pf max) can be charged/discharged by the external source. the internal resistance of the analog source must allow the capacitance to reach its final voltage level within t s. after the end of the sample time t s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t s depend o n programming. (2) tested in production
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 electric al characteristics docid025118 rev 4 85 / 101 table 55: adc accuracy with rain < 10 k , vdd= 5 v symbol parameter conditions typ max (1) unit |e t | total unadjusted error (2) f adc = 2 mhz 1.6 3.5 lsb f adc = 4 mhz 2.2 4 f adc = 6 mhz 2.4 4.5 |e o | offset error (2) f adc = 2 mhz 1.1 2.5 f adc = 4 mhz 1.5 3 f adc = 6 mhz 1.8 3 |e g | gain error (2) f adc = 2 mhz 1.5 3 f adc = 4 mhz 2.1 3 f adc = 6 mhz 2.2 4 |e d | differential linearity error (2) f adc = 2 mhz 0.7 1.5 f adc = 4 mhz 0.7 1.5 f adc = 6 mhz 0.7 1.5 |e l | integral linearity error (2) f adc = 2 mhz 0.6 1.5 f adc = 4 mhz 0.8 2 f adc = 6 mhz 0.8 2 notes: (1) data based on characterisation results, not tested in production. (2) adc accuracy vs. n egative injection current: injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in the i/o port pin characteristics section does not affect the adc accuracy.
electrical characteristics stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 86 / 101 docid025118 re v 4 tabl e 56: adc accuracy with rain < 10 k rain, vdd = 3.3 v symbol parameter conditions typ max (1) unit |e t | total unadjusted error f adc = 2 mhz 1.6 3.5 lsb f adc = 4 mhz 1.9 4 |e o | offset err or f adc = 2 mhz 1 2.5 f adc = 4 mhz 1.5 2.5 |e g | gain error f adc = 2 mhz 1.3 3 f adc = 4 mhz 2 3 |e d | differential linearity error f adc = 2 mhz 0.7 1 f adc = 4 mhz 0.7 1.5 |e l | integral lineari ty error f adc = 2 mhz 0.6 1.5 f adc = 4 mhz 0.8 2 notes: (1) data based on characterisation results, not tested in production. figure 40 : adc accuracy characteristics 1. example of an actual transfer curve. 2. the ideal transfer curve 3. end point correlation line e t = total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o = offset error: deviation between the first actual transition and the first ideal one. e g = gain error: deviation between the last ideal transition and the last actual one. e d = differential linearity error: maximum deviation between actual steps and the ideal
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 electrical characteristics docid025118 rev 4 87 / 101 one. e l = integral linearity error: maximum deviation between any actual transition and the end p oint correlation line. figure 41 : typical application with adc 9.3.11 emc characteristics susceptibility tests are performed on a sample basis during product characterization. 9.3.11.1 functional ems (electromagnetic susceptibility) while executing a simple application (toggling 2 leds through i/o po rts), the product is stressed by two electromagnetic events until a failure occurs (indicated by the leds). ? fesd: functional electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. this t est conforms with the iec 61000 - 4 - 2 standard. ? ftb: a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test conforms with the iec 61000 - 4 - 4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709 (emc design guide for stmicrocontrollers). 9.3.11.2 designing hardened software to avoid noi se problems emc characterization and optimization are performed at component level with a typical application environment and simplified m cu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with t he emc level requested for his application. stm8 10-bit a/d co n v ersion r ain c ain v ain ainx v dd v t 0.6 v v t 0.6 v i l 1 a c adc
electrical characteristics stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 88 / 101 docid025118 re v 4 prequalification trials most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring. see application note an1015 (software tec hniques for improving microcontroller emc performance). table 57: ems data symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, t a = 25 c, f master = 16 mhz (hsi clock), conforming to iec 61000 - 4 - 2 2/b (1) v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, t a = 25 c ,f master = 16 m hz (hsi clock),conforming to iec 61000 - 4 - 4 4/a (1) notes: (1) data obtained with hsi clock configuration, after applying hw recommendations described in an2860 (emc guidelines for stm8s microcontrollers). 9.3.11.3 electrom agnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emission. this emission test is in line with the norm sae iec 61967 - 2 which specifies the board and the loading of each pin. table 58: emi data symbol parameter conditions unit general conditions monitored frequency band max f hse /f cpu (1) 16 mhz/8 mhz 16 mhz/16 mhz s emi peak level v dd = 5 v, t a = 25 c, lqfp32 package. conforming to sae iec 61967 - 2 0.1 mhz to 30 mhz 5 5 dbv 30 mhz to 130 mhz 4 5 130 mhz to 1 ghz 5 5 sae emi level sae emi level 2.5 2.5 - notes: (1) data based on characterisation results, not tested in production.
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 electrical characteristics docid025118 rev 4 89 / 101 9.3.11.4 absolute maximum ratings (electrical sensitivity) based on three different tests (esd, dlu and lu) using specific measurement methods, the product is stressed to determine its performance in terms of electrical sensitivity. for more details, refer to the application note an1181 . 9.3.11.5 electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample accordin g to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). one model can be simulated: human body model. this test conforms to the jesd22 - a114a/a115a standard. for more details, refer to the ap plication note an1181. table 59: esd absolute maximum ratings symbol ratings conditions clas s maximu m value (1) un it v esd(hbm) electrostatic discharge voltage (human body model) t a = 25c, conforming to jesd22 - a114 3a 4000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = 25c, conforming to jesd22 - c101 3 500 v esd(mm) electrostatic discharge voltage (machine model) t a = 25c, conforming to jesd22 - a115 b 200 notes: ( 1) data based on characterization results, not tested in production
electrical characteristics stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 90 / 101 docid025118 re v 4 9.3.11.6 static latch - up two complementary static tests are required on six parts to assess the latch - up perfor mance: ? a supply overvoltage (applied to each power supply pin) ? a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch - up standard. for more details, refer to the application note an1181. table 60: electrical sensitivities symbol parameter conditions class (1) lu static latch - up class t a = 25 c a t a = 85 c a t a = 125 c a t a = 150 c a notes: (1) class description: a class is an stmicroelectronics internal specification. all its limits are higher than the jedec specifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jede c criteria (international standard).
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 package information docid025118 rev 4 91 / 101 10 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, dependin g on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 10.1 32 - pin lqfp package mechanical data figure 42 : 32 - pin low profile quad flat package (7 x 7) table 61: 32 - pin low profile quad flat package mechanical data dim. mm inches (1) m in typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 0.200 0.0035 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 5.600 0.2205 e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 5.600 0.2205 e 0.800 0.0315 l 0.450 0.600 0.750 0.0177 0.0236 0.0295
package information stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 92 / 101 docid025118 re v 4 dim. mm inches (1) m in typ max min typ max l1 1.000 0.0394 k 0.0 3.5 7.0 0.0 3.5 7.0 ccc 0.100 0.0039 notes: (1) values in inches are converted from mm an d rounded to 4 decimal digits 10.2 20 - pin tssop package mechanical data figure 43 : 20 - pin, 4.40 mm body, 0.65 mm pitch table 62: 20 - pin, 4.40 mm body, 0.65 mm pitch mechanical data dim. mm inches (1) min typ max min typ max a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 0.800 1.000 1.050 0.0315 0.0394 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 d (2) 6.400 6.500 6.600 0.2520 0.2559 0.2598 e 6.200 6.400 6.600 0.2441 0.2520 0.2598 e1 (3) 4.300 4.400 4.500 0.1693 0.1732 0.1772 e 0.650 0.0256 l 0.450 0.600 0.750 0.0177 0.0236 0.0295
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 package information docid025118 rev 4 93 / 101 dim. mm inches (1) min typ max min typ max l1 1.000 0.0394 k 0.0 8.0 0.0 8.0 aaa 0.100 0.0039 notes: (1) values in inches are converted from mm and rounded to 4 decimal digits (2) dimension "d" does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. (3) dimension "e1" does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.25mm per side.
thermal characteristics stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 94 / 101 docid025118 re v 4 11 thermal characteristics the maximum chip junction temper ature (t jmax ) must never exceed the values given in section 8.1: "memory map" . the maximum chip - junction temperature, t jmax , in degrees celsius, may be calculated using the following equation: t jmax = t amax + (p dmax x j a ) where: ? t amax is the maximum ambient temperature in c ? ja is the package junction - to - ambient thermal resistance in c/w ? p dmax is the sum of p intmax and p i/omax (pdmax = p intmax + p i/omax ) ? p intmax is the product of i dd andv dd , expressed in watts. t his is the maximum chip internal power. ? p i/omax represents the maximum power dissipation on output pins where: p i/omax = (v ol *i ol ) + ((v dd - v oh) *i oh ), taking into account the actual v ol /i ol and v oh /i oh of the i/os at low and high level in the applicat ion. table 63: thermal characteristics symbol parameter (1) value unit ja thermal resistance junction - ambient tssop20 - 4 x 4 mm 110 c/w ja thermal resistance junction - ambient lqfp32 - 7 x 7 mm 60 c/w notes: (1) thermal resistances are based on jedec jesd51 - 2 with 4 - layer pcb in a natural convection environment. 11.1 reference document jesd51 - 2 integrated circuits t hermal test method environment conditions - natural convection (still air). available from www.jedec.org.
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 thermal characteristics docid025118 rev 4 95 / 101 11.2 selecting the product temperature range when o rdering the microcontroller, the temperature range is specified in the order code. the following example shows how to calculate the temperature range needed for a given application. assuming the following application conditions: ? maximum ambient temperat ure t amax = 75 c (measured according to jesd51 - 2) ? i ddmax = 8 ma, v dd = 5 v ? maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v p intmax = 8 ma x 5 v = 400 mw amax ? p dmax = 400 mw + 64 mw thus: p dmax = 464 mw t jmax for lqfp32 can be calculated as follows, using the thermal resistance ja : t jmax = 75 c + (60 c/w x 464 mw) = 75 c + 27.8 c = 102.8 c this is within the range of the suffix 6 version parts ( - 40 < t j < 105 c). in this case, parts must be ordered a t least with the temperature range suffix 6.
ordering information stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 96 / 101 docid025118 re v 4 12 ordering information figure 44 : ordering information scheme 1. for a list of available op tions (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the st sales office nearest to you. product class program memory size 1 = 4 kbytes example: device family 62 = lin only f = flash + eeprom program memory type t emperature range a = -40 c to 85 c pin count 3 = 20 pins 6 = 32 pins packing y = t ray u = t ube stm8 a f 62 2 3 p u 8-bit automotive microcontroller c number of adc analog inputs blank = 5 analog inputs a = 7 analog inputs c = -40 c to 125c d = -40 c to 150c a package type t = lqf p p = tsso p 2 = 8 kbytes x = t ape and reel compliant with ei a 481-c
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 stm8 development tools docid025118 rev 4 97 / 101 13 stm8 development tools development tools for the stm8 microcontrollers include the full - featured stice emulation system supported by a complete software tool package including c compiler, assembler and integrated development environm ent with high - level language debugger. in addition, the stm8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low - cost in - circuit debugger/programmer. 13.1 emulation and in - circuit debugging tools the stice emulation system offers a complete range of emulation and in - circuit debugging features on a platform that is designed for versatility and cost - effectiveness. in addition, stm8 application development is supported by a low - cost in - circuit debugger/programmer. the stice is the fourth generation of full featured emulators from stmicroelectronics. it offers new advanced debugging capabilities inclu ding profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application. in addition, stice offers in - circuit debugging and programming of stm8 microcontrollers via the stm8 single wire i nterface module (swim), which allows non - intrusive debugging of an application while it runs on the target microcontroller. for improved cost effectiveness, stice is based on a modular design that allows you to order exactly what you need to meet your dev elopment requirements and to adapt your emulation system to support existing and future st microcontrollers. stice key features ? occurrence and time profiling and code coverage (new features) ? advanced breakpoints with up to 4 levels of conditions ? data br eakpoints ? program and data trace recording up to 128 kb records ? read/write on the fly of memory during emulation ? in - circuit debugging/programming via swim protocol ? 8 - bit probe analyzer ? 1 input and 2 output triggers ? power supply follower managing appl ication voltages between 1.62 to 5.5 v ? modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements ? supported by free software tools that include integrated development environment ( ide), programming software interface and assembler for stm8.
stm8 development tools stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 98 / 101 docid025118 re v 4 13.2 software tools stm8 development tools are supported by a complete, free software package from stmicroelectronic s that includes st visual develop (stvd) ide and the st visual programmer (stvp) software interface. stvd provides seamless integration of the cosmic and raisonance c compilers for stm8, which are available in a free version that outputs up to 16 kbytes of code. 13.2.1 stm8 toolset stm8 toolset with stvd integrated development environment and stvp programming software is available for free download at www.st.com/mcu. this package inclu des: st visual develop C full - featured integrated development environment from st, featuring ? seamless integration of c and asm toolsets ? full - featured debugger ? project management ? syntax highlighting editor ? integrated programming interface ? support of advanced emulation features for stice such as code profiling and coverage st visual programmer (stvp) C easy - to - use, unlimited graphical interface allowing read, write and verify of your stm8 microcontrollers flash program memory, data eeprom and option bytes. stvp also offers project mode for saving programming configurations and automating programming sequences. 13.2.2 c and assembly toolchains control of c and assembly toolchains is seamlessly integrated into the stvd integrated development environment, making it possible to configure and control the building of your application directly from an easy - to - use graphical interface. available toolchains include: ? cosmic c c ompiler for stm8 all compilers are available in free version with a limited code size depending on the compiler. for more information, refer to www.cosmic - software.com, www.raisonance.com, and www.iar.com. ? stm8 assembler linker free assembly toolchain inc luded in the stm8 toolset, which allows you to assemble and link your application source code. 13.3 programming tools during the development cycle, stice provides in - circuit pr ogramming of the stm8 flash microcontroller on your application board via the swim protocol. additional tools are to include a low - cost in - circuit programmer as well as st socket boards, which provide dedicated programming platforms with sockets for progra mming your stm8. for production environments, programmers will include a complete range of gang and automated programming solutions from third - party tool developers already supplying programmers for the stm8 family.
st m8af6213 STM8AF6223 STM8AF6223a stm8af6226 revision history docid025118 rev 4 99 / 101 14 revision history table 64: document revision history date revision changes 11 - oct - 2013 1 initial release. 16 - dec - 2013 2 changed datasheet status to production data. updated figure STM8AF6223pxax tssop20 pinout to add spi_nss to pd4, tli to pd2, and change remap function on pb5 from tim5_bkin to tim1_bkin. updated table STM8AF6223pxax tssop20 pin description to add spi_ns s to pd4 and tli to pd2. updated table STM8AF6223 tssop20 pin description and table lqfp32 pin description . updated afr2 definition in STM8AF6223pxax al ternate function remapping bits [7:2] for 20 - pin packages removed remapping option on pa3 for afr[1:0]=10 in table STM8AF6223pxax alternate function remapping bits [1:0] for 20 - pin packages . added note and removed remapp ing option on pa3 for afr[1:0]=11 in table STM8AF6223 alternate function remapping bits [1:0] for 20 - pin packages . updated afr2 definition in STM8AF6223 alternate function remapping bits [ 7:2] for 20 - pin packages . added note below table stm8af6226t alternate function remapping bits [1:0] for 32 - pin packages . updated table i2c characteristics to modify th(sda) and add ts p. updated section c assembly toolchains .
revision history stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 100 / 101 docid025118 re v 4 date revision changes 03 - apr - 2014 3 replaced stm8af6226t by stm8af6226 part number. added STM8AF6223a part number to cover STM8AF6223pxax order codes. removed linuart alternate function for pa3 in table "STM8AF6223pxax tssop20 pin description" . removed note 3 for idd(ah) in table "total current consumption in active halt mode at vdd = 5 v". updated remapping option on pa3 for afr[1:0]=11 in table "STM8AF6223 alternate function remapping bits [1:0] for 20 - pin packages". updated notes related to tret minimum value in table "data memory". updated table "esd absolute maximum ratings". added notes related to protrusions and gate burrs for d and e1 dimensions in table "20 - pin, 4.40 mm body, 0.65 mm pit ch mechanical data". 1 1 - jul - 2014 4 extended the applicability to stm8af6213 devices. updated the program memory feature, the power management, and the clock management features on the cover page. added the table in the section "memory map". updated the figure "fcpumax versus vdd" in the section "operating conditions". updated the ordering information.
stm8af6213 STM8AF6223 STM8AF6223a stm8af6226 docid025118 rev 4 101 / 101 important notice C please read carefully stmicroelectronics nv and i ts subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of order acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void a ny warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics C all rights reserved

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